X-Git-Url: http://wien.tomnetworks.com/gitweb/?a=blobdiff_plain;f=src%2Fmainboard%2Famd%2Ftilapia_fam10%2Fromstage.c;h=52cab42eb4abc18d2e0306137e084f5c80970dc5;hb=5ff7c13e858a31addf1558731a12cf6c753b576d;hp=7408a3f8a1d40911ca90680e1332a95b61bc079d;hpb=e5b7507882d4ee042d9c4d03e2e763bb49774b43;p=coreboot.git diff --git a/src/mainboard/amd/tilapia_fam10/romstage.c b/src/mainboard/amd/tilapia_fam10/romstage.c index 7408a3f8a..52cab42eb 100644 --- a/src/mainboard/amd/tilapia_fam10/romstage.c +++ b/src/mainboard/amd/tilapia_fam10/romstage.c @@ -21,19 +21,10 @@ #define SYSTEM_TYPE 1 /* DESKTOP */ //#define SYSTEM_TYPE 2 /* MOBILE */ -#define SET_NB_CFG_54 1 - -//used by raminit -#define QRANK_DIMM_SUPPORT 1 - //used by incoherent_ht #define FAM10_SCAN_PCI_BUS 0 #define FAM10_ALLOCATE_IO_RANGE 0 -//used by init_cpus and fidvid -#define SET_FIDVID 1 -#define SET_FIDVID_CORE_RANGE 0 - #include #include #include @@ -47,70 +38,47 @@ #include "northbridge/amd/amdfam10/raminit.h" #include "northbridge/amd/amdfam10/amdfam10.h" #include - #include "cpu/x86/lapic/boot_cpu.c" #include "northbridge/amd/amdfam10/reset_test.c" - #include #include "cpu/x86/bist.h" - -static int smbus_read_byte(u32 device, u32 address); - -#include "superio/ite/it8718f/it8718f_early_serial.c" -#include - +#include "superio/ite/it8718f/early_serial.c" #include "cpu/x86/mtrr/earlymtrr.c" #include #include "northbridge/amd/amdfam10/setup_resource_map.c" - -#include "southbridge/amd/rs780/rs780_early_setup.c" -#include "southbridge/amd/sb700/sb700_early_setup.c" +#include "southbridge/amd/rs780/early_setup.c" +#include "southbridge/amd/sb700/sb700.h" +#include "southbridge/amd/sb700/smbus.h" #include "northbridge/amd/amdfam10/debug.c" -static void activate_spd_rom(const struct mem_controller *ctrl) -{ -} +static void activate_spd_rom(const struct mem_controller *ctrl) { } static int spd_read_byte(u32 device, u32 address) { - int result; - result = smbus_read_byte(device, address); - return result; + return do_smbus_read_byte(SMBUS_IO_BASE, device, address); } #include "northbridge/amd/amdfam10/amdfam10.h" - #include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c" -#include "northbridge/amd/amdfam10/amdfam10_pci.c" - +#include "northbridge/amd/amdfam10/pci.c" #include "resourcemap.c" #include "cpu/amd/quadcore/quadcore.c" - #include "cpu/amd/car/post_cache_as_ram.c" #include "cpu/amd/microcode/microcode.c" + +#if CONFIG_UPDATE_CPU_MICROCODE #include "cpu/amd/model_10xxx/update_microcode.c" -#include "cpu/amd/model_10xxx/init_cpus.c" +#endif +#include "cpu/amd/model_10xxx/init_cpus.c" #include "northbridge/amd/amdfam10/early_ht.c" -#include "southbridge/amd/sb700/sb700_early_setup.c" - -//#include "spd_addr.h" - -#define RC00 0 -#define RC01 1 - -#define DIMM0 0x50 -#define DIMM1 0x51 -#define DIMM2 0x52 -#define DIMM3 0x53 +#include void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { - struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); static const u8 spd_addr[] = {RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, }; - u32 bsp_apicid = 0; - u32 val; + u32 bsp_apicid = 0, val; msr_t msr; if (!cpu_init_detectedx && boot_cpu()) { @@ -119,8 +87,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) /* mov bsp to bus 0xff when > 8 nodes */ set_bsp_node_CHtExtNodeCfgEn(); enumerate_ht_chain(); - - sb700_pci_port80(); + sb7xx_51xx_pci_port80(); } post_code(0x30); @@ -133,18 +100,11 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x32); enable_rs780_dev8(); - sb700_lpc_init(); + sb7xx_51xx_lpc_init(); it8718f_enable_serial(0, CONFIG_TTYS0_BASE); - uart_init(); - -#if CONFIG_USBDEBUG - sb700_enable_usbdebug(CONFIG_USBDEBUG_DEFAULT_PORT); - early_usbdebug_init(); -#endif console_init(); - printk(BIOS_DEBUG, "\n"); // dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE); @@ -161,7 +121,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) /* Setup sysinfo defaults */ set_sysinfo_in_ram(0); +#if CONFIG_UPDATE_CPU_MICROCODE update_microcode(val); +#endif post_code(0x33); cpuSetAMDMSR(); @@ -185,21 +147,21 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) */ wait_all_core0_started(); - #if CONFIG_LOGICAL_CPUS==1 +#if CONFIG_LOGICAL_CPUS==1 /* Core0 on each node is configured. Now setup any additional cores. */ printk(BIOS_DEBUG, "start_other_cores()\n"); start_other_cores(); post_code(0x37); wait_all_other_cores_started(bsp_apicid); - #endif +#endif post_code(0x38); /* run _early_setup before soft-reset. */ rs780_early_setup(); - sb700_early_setup(); + sb7xx_51xx_early_setup(); - #if SET_FIDVID == 1 +#if CONFIG_SET_FIDVID msr = rdmsr(0xc0010071); printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo); @@ -220,7 +182,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) /* show final fid and vid */ msr=rdmsr(0xc0010071); printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo); - #endif +#endif rs780_htinit(); @@ -252,17 +214,47 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) dump_pci_device_range(PCI_DEV(0, 0x18, 3), 0, 0x200); */ -// ram_check(0x00200000, 0x00200000 + (640 * 1024)); -// ram_check(0x40200000, 0x40200000 + (640 * 1024)); - - // die("After MCT init before CAR disabled."); rs780_before_pci_init(); - sb700_before_pci_init(); + sb7xx_51xx_before_pci_init(); post_code(0x42); printk(BIOS_DEBUG, "\n*** Yes, the copy/decompress is taking a while, FIXME!\n"); post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB. post_code(0x43); // Should never see this post code. } + +/** + * BOOL AMD_CB_ManualBUIDSwapList(u8 Node, u8 Link, u8 **List) + * Description: + * This routine is called every time a non-coherent chain is processed. + * BUID assignment may be controlled explicitly on a non-coherent chain. Provide a + * swap list. The first part of the list controls the BUID assignment and the + * second part of the list provides the device to device linking. Device orientation + * can be detected automatically, or explicitly. See documentation for more details. + * + * Automatic non-coherent init assigns BUIDs starting at 1 and incrementing sequentially + * based on each device's unit count. + * + * Parameters: + * @param[in] u8 node = The node on which this chain is located + * @param[in] u8 link = The link on the host for this chain + * @param[out] u8** list = supply a pointer to a list + * @param[out] BOOL result = true to use a manual list + * false to initialize the link automatically + */ +BOOL AMD_CB_ManualBUIDSwapList (u8 node, u8 link, const u8 **List) +{ + static const u8 swaplist[] = { 0xFF, CONFIG_HT_CHAIN_UNITID_BASE, CONFIG_HT_CHAIN_END_UNITID_BASE, 0xFF }; + /* If the BUID was adjusted in early_ht we need to do the manual override */ + if ((CONFIG_HT_CHAIN_UNITID_BASE != 0) && (CONFIG_HT_CHAIN_END_UNITID_BASE != 0)) { + printk(BIOS_DEBUG, "AMD_CB_ManualBUIDSwapList()\n"); + if ((node == 0) && (link == 0)) { /* BSP SB link */ + *List = swaplist; + return 1; + } + } + + return 0; +}