X-Git-Url: http://wien.tomnetworks.com/gitweb/?a=blobdiff_plain;f=src%2Fmainboard%2Famd%2Fserengeti_cheetah_fam10%2FOptions.lb;h=e2963954fed5e4122fa566938aad6783e584fb4b;hb=743b635ca3c89b78876095c7f61869104f9ab1b0;hp=cb68daa18175cbfbb681db99a5302461e7f517c5;hpb=7e61e45402aba2b90997f4f02ca8266cf65a229a;p=coreboot.git

diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/Options.lb b/src/mainboard/amd/serengeti_cheetah_fam10/Options.lb
index cb68daa18..e2963954f 100644
--- a/src/mainboard/amd/serengeti_cheetah_fam10/Options.lb
+++ b/src/mainboard/amd/serengeti_cheetah_fam10/Options.lb
@@ -18,8 +18,10 @@
 #
 
 uses HAVE_MP_TABLE
+uses CONFIG_ROMFS
 uses HAVE_PIRQ_TABLE
 uses HAVE_ACPI_TABLES
+uses HAVE_ACPI_RESUME
 uses ACPI_SSDTX_NUM
 uses USE_FALLBACK_IMAGE
 uses USE_FAILOVER_IMAGE
@@ -59,7 +61,7 @@ uses MAINBOARD_VENDOR
 uses MAINBOARD
 uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
 uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-uses LINUXBIOS_EXTRA_VERSION
+uses COREBOOT_EXTRA_VERSION
 uses _RAMBASE
 uses TTYS0_BAUD
 uses TTYS0_BASE
@@ -75,7 +77,6 @@ uses CROSS_COMPILE
 uses CC
 uses HOSTCC
 uses OBJCOPY
-uses CONFIG_CHIP_NAME
 uses CONFIG_CONSOLE_VGA
 uses CONFIG_PCI_ROM_RUN
 uses HW_MEM_HOLE_SIZEK
@@ -114,6 +115,7 @@ uses CONFIG_AMDMCT
 
 uses CONFIG_USE_PRINTK_IN_CAR
 uses CAR_FAM10
+uses AMD_UCODE_PATCH_FILE
 
 ###
 ### Build options
@@ -147,7 +149,7 @@ default HAVE_FALLBACK_BOOT=1
 default HAVE_FAILOVER_BOOT=1
 
 ##
-## Build code to reset the motherboard from linuxBIOS
+## Build code to reset the motherboard from coreboot
 ##
 default HAVE_HARD_RESET=1
 
@@ -174,7 +176,7 @@ default ACPI_SSDTX_NUM=31
 default HAVE_OPTION_TABLE=1
 
 ##
-## Move the default LinuxBIOS cmos range off of AMD RTC registers
+## Move the default coreboot cmos range off of AMD RTC registers
 ##
 default LB_CKS_RANGE_START=49
 default LB_CKS_RANGE_END=122
@@ -195,9 +197,6 @@ default ENABLE_APIC_EXT_ID=1
 default APIC_ID_OFFSET=0x00
 default LIFT_BSP_APIC_ID=1
 
-#CHIP_NAME ?
-default CONFIG_CHIP_NAME=1
-
 #memory hole size, 0 mean disable, others will enable the hole, at that case if it is small than mmio_basek, it will use mmio_basek instead.
 #2G
 #default HW_MEM_HOLE_SIZEK=0x200000
@@ -260,11 +259,20 @@ default MAINBOARD_VENDOR="AMD"
 default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x1022
 default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2b80
 
+##
+## Set microcode patch file name
+##
+##	Barcelona rev Ax:  "mc_patch_01000020.h"
+##	Barcelona rev B0, B1, BA: "mc_patch_01000084.h"
+##	Barcelona rev B2, B3: "mc_patch_01000083.h"
+##
+default AMD_UCODE_PATCH_FILE="mc_patch_01000083.h"
+
 ###
-### LinuxBIOS layout values
+### coreboot layout values
 ###
 
-## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
+## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
 default ROM_IMAGE_SIZE = 65536
 
 ##
@@ -283,7 +291,7 @@ default HEAP_SIZE=0xc0000
 default USE_OPTION_TABLE = (!USE_FALLBACK_IMAGE) && (!USE_FAILOVER_IMAGE )
 
 ##
-## LinuxBIOS C code runs at this location in RAM
+## Coreboot C code runs at this location in RAM
 ##
 default _RAMBASE=0x00200000
 
@@ -334,7 +342,7 @@ default TTYS0_BASE=0x3f8
 default TTYS0_LCS=0x3
 
 ##
-### Select the linuxBIOS loglevel
+### Select the coreboot loglevel
 ##
 ## EMERG      1   system is unusable
 ## ALERT      2   action must be taken immediately
@@ -356,4 +364,9 @@ default  MAXIMUM_CONSOLE_LOGLEVEL=8
 default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
 
 ### End Options.lb
+#
+# ROMFS
+#
+#
+default CONFIG_ROMFS=0
 end