X-Git-Url: http://wien.tomnetworks.com/gitweb/?a=blobdiff_plain;f=src%2Fmainboard%2Famd%2Fpistachio%2Fromstage.c;h=187eb207c214d1bc77a7a34e1f65e5cb89c03b44;hb=7b997053eb2fcde464f5f6a1e5c85d1ffb6b4e32;hp=18a4d263bf6a2c3b674dfff6c2b6330ce6a5ef9d;hpb=57b2ff886e0ce2c92820f5722c8031def3ac94cf;p=coreboot.git

diff --git a/src/mainboard/amd/pistachio/romstage.c b/src/mainboard/amd/pistachio/romstage.c
index 18a4d263b..187eb207c 100644
--- a/src/mainboard/amd/pistachio/romstage.c
+++ b/src/mainboard/amd/pistachio/romstage.c
@@ -42,17 +42,9 @@
 #include "southbridge/amd/sb600/sb600_early_setup.c"
 #include "northbridge/amd/amdk8/debug.c" /* After sb600_early_setup.c! */
 
-/* CAN'T BE REMOVED! memory bus reset hook for some broken amd k8 boards. */
-static void memreset(int controllers, const struct mem_controller *ctrl)
-{
-}
-
-/* called in raminit_f.c */
-static inline void activate_spd_rom(const struct mem_controller *ctrl)
-{
-}
+static void memreset(int controllers, const struct mem_controller *ctrl) { }
+static void activate_spd_rom(const struct mem_controller *ctrl) { }
 
-/*called in raminit_f.c */
 static inline int spd_read_byte(u32 device, u32 address)
 {
 	return smbus_read_byte(device, address);
@@ -85,14 +77,12 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 		/* Nothing special needs to be done to find bus 0 */
 		/* Allow the HT devices to be found */
 		enumerate_ht_chain();
-
 		sb600_lpc_port80();
 		/* sb600_pci_port80(); */
 	}
 
-	if (bist == 0) {
+	if (bist == 0)
 		bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
-	}
 
 	enable_rs690_dev8();
 	sb600_lpc_init();
@@ -138,8 +128,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	/* Check to see if processor is capable of changing FIDVID  */
 	/* otherwise it will throw a GP# when reading FIDVID_STATUS */
 	cpuid1 = cpuid(0x80000007);
-	if( (cpuid1.edx & 0x6) == 0x6 ) {
-
+	if ((cpuid1.edx & 0x6) == 0x6) {
 		/* Read FIDVID_STATUS */
 		msr=rdmsr(0xc0010042);
 		printk(BIOS_DEBUG, "begin msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo);
@@ -151,7 +140,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 		/* show final fid and vid */
 		msr=rdmsr(0xc0010042);
 		printk(BIOS_DEBUG, "end msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo);
-
 	} else {
 		printk(BIOS_DEBUG, "Changing FIDVID not supported\n");
 	}