X-Git-Url: http://wien.tomnetworks.com/gitweb/?a=blobdiff_plain;f=src%2Fmainboard%2Famd%2Fmahogany_fam10%2Fromstage.c;h=616154853569e14f174a95286ff835b1b38fd286;hb=57b2ff886e0ce2c92820f5722c8031def3ac94cf;hp=5b062d61fffab7ff03b42e251f0b3c5775bd0deb;hpb=5244e1ba63e5f3ea12066734bfb0d864a8f1f11d;p=coreboot.git diff --git a/src/mainboard/amd/mahogany_fam10/romstage.c b/src/mainboard/amd/mahogany_fam10/romstage.c index 5b062d61f..616154853 100644 --- a/src/mainboard/amd/mahogany_fam10/romstage.c +++ b/src/mainboard/amd/mahogany_fam10/romstage.c @@ -38,22 +38,16 @@ #include "northbridge/amd/amdfam10/raminit.h" #include "northbridge/amd/amdfam10/amdfam10.h" #include - #include "cpu/x86/lapic/boot_cpu.c" #include "northbridge/amd/amdfam10/reset_test.c" - #include #include "cpu/x86/bist.h" - static int smbus_read_byte(u32 device, u32 address); - #include "superio/ite/it8718f/it8718f_early_serial.c" #include - #include "cpu/x86/mtrr/earlymtrr.c" #include #include "northbridge/amd/amdfam10/setup_resource_map.c" - #include "southbridge/amd/rs780/rs780_early_setup.c" #include "southbridge/amd/sb700/sb700_early_setup.c" #include "northbridge/amd/amdfam10/debug.c" @@ -71,18 +65,14 @@ static int spd_read_byte(u32 device, u32 address) } #include "northbridge/amd/amdfam10/amdfam10.h" - #include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c" #include "northbridge/amd/amdfam10/amdfam10_pci.c" - #include "resourcemap.c" #include "cpu/amd/quadcore/quadcore.c" - #include "cpu/amd/car/post_cache_as_ram.c" #include "cpu/amd/microcode/microcode.c" #include "cpu/amd/model_10xxx/update_microcode.c" #include "cpu/amd/model_10xxx/init_cpus.c" - #include "northbridge/amd/amdfam10/early_ht.c" #include "southbridge/amd/sb700/sb700_early_setup.c" @@ -247,4 +237,3 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB. post_code(0x43); // Should never see this post code. } -