X-Git-Url: http://wien.tomnetworks.com/gitweb/?a=blobdiff_plain;f=src%2Fhistory.vhd;h=ca9800f1dd5140b7307e936523f460a52fd30e67;hb=9f86188ebcedaf3cc7a7106b0a8d6a96493d41bc;hp=3031c22ed899154be4109ff36bd58b8dc99764b8;hpb=4d6cc6ba70abf036904d501afb7fea6d059c5297;p=hwmod.git diff --git a/src/history.vhd b/src/history.vhd index 3031c22..ca9800f 100644 --- a/src/history.vhd +++ b/src/history.vhd @@ -17,71 +17,233 @@ entity history is -- Display d_new_eingabe : out std_logic; d_new_result : out std_logic; + d_new_bs : out std_logic; d_zeile : in hzeile; d_spalte : in hspalte; d_get : in std_logic; d_done : out std_logic; - d_char : out hbyte + d_char : out hbyte; -- Parser -- TODO: pins + + -- TODO: tmp only! + do_it : in std_logic; + finished : out std_logic ); end entity history; architecture beh of history is - type HISTORY_STATE is (SIDLE); + type HISTORY_STATE is (SIDLE, S_S_INIT, S_S_WRITE, S_S_BS, S_S_DONE, S_S_FIN, + S_D_INIT, S_D_READ, S_S_FIN_POSUP); signal state_int, state_next : HISTORY_STATE; + signal was_bs_int, was_bs_next : std_logic; + signal pos_int, pos_next : std_logic_vector(H_RAM_WIDTH - 1 downto 0); signal s_done_int, s_done_next : std_logic; + signal s_cnt_int, s_cnt_next : hspalte; signal d_new_eingabe_int, d_new_eingabe_next : std_logic; signal d_new_result_int, d_new_result_next : std_logic; + signal d_new_bs_int, d_new_bs_next: std_logic; signal d_done_int, d_done_next : std_logic; signal d_char_int, d_char_next : hbyte; + + signal finished_int, finished_next : std_logic; + + -- ram + signal address_next, address_int : std_logic_vector(H_RAM_WIDTH - 1 downto 0); + signal data_out, data_in_next, data_in_int : hbyte; + signal wr_next, wr_int : std_logic; begin s_done <= s_done_int; d_new_eingabe <= d_new_eingabe_int; d_new_result <= d_new_result_int; + d_new_bs <= d_new_bs_int; d_done <= d_done_int; d_char <= d_char_int; + finished <= finished_int; + process(sys_clk, sys_res_n) begin if sys_res_n = '0' then -- internal state_int <= SIDLE; + was_bs_int <= '0'; + pos_int <= (others => '0'); -- out s_done_int <= '0'; + s_cnt_int <= (0 => '1', others => '0'); d_new_result_int <= '0'; d_new_eingabe_int <= '0'; + d_new_bs_int <= '0'; d_done_int <= '0'; d_char_int <= (others => '0'); + + finished_int <= '0'; + + address_int <= (0 => '1', others => '0'); + data_in_int <= x"00"; + wr_int <= '0'; elsif rising_edge(sys_clk) then -- internal state_int <= state_next; + was_bs_int <= was_bs_next; + pos_int <= pos_next; -- out s_done_int <= s_done_next; + s_cnt_int <= s_cnt_next; d_new_result_int <= d_new_result_next; d_new_eingabe_int <= d_new_eingabe_next; + d_new_bs_int <= d_new_bs_next; d_done_int <= d_done_next; d_char_int <= d_char_next; + + finished_int <= finished_next; + + address_int <= address_next; + data_in_int <= data_in_next; + wr_int <= wr_next; end if; end process; -- next state - process(state_int) + process(state_int, d_get, do_it, s_take, s_backspace, was_bs_int) begin state_next <= state_int; case state_int is when SIDLE => - null; + -- S_S_FIN: tmp.. + if s_take = '1' then + state_next <= S_S_INIT; + elsif do_it = '1' then + state_next <= S_S_FIN; + elsif d_get = '1' then + state_next <= S_D_INIT; + end if; + when S_S_INIT => + if s_backspace = '1' then + state_next <= S_S_BS; + else + state_next <= S_S_WRITE; + end if; + when S_S_WRITE => + state_next <= S_S_DONE; + when S_S_BS => + state_next <= S_S_DONE; + when S_S_FIN => + if do_it = '0' then + state_next <= S_S_FIN_POSUP; + end if; + when S_S_FIN_POSUP => + state_next <= SIDLE; + when S_S_DONE => + if s_take = '0' then + state_next <= SIDLE; + end if; + + when S_D_INIT => + state_next <= S_D_READ; + when S_D_READ => + if d_get = '0' then + state_next <= SIDLE; + end if; end case; end process; -- out - process(state_int) + process(state_int, s_cnt_int, d_spalte, d_zeile, data_out, s_char, address_int, + data_in_int, d_new_result_int, d_new_eingabe_int, d_new_bs_int, + was_bs_int, s_take, pos_int) + variable addr_tmp : std_logic_vector(H_RAM_WIDTH - 1 downto 0); + variable mul_tmp : std_logic_vector((H_RAM_WIDTH*2) -1 downto 0); begin + s_done_next <= '0'; + s_cnt_next <= s_cnt_int; + was_bs_next <= was_bs_int; + pos_next <= pos_int; + d_new_result_next <= d_new_result_int; + d_new_eingabe_next <= d_new_eingabe_int; + d_new_bs_next <= '0'; + d_done_next <= '0'; + d_char_next <= (others => '0'); + finished_next <= '0'; + wr_next <= '0'; + address_next <= address_int; + data_in_next <= data_in_int; + case state_int is when SIDLE => + -- TODO: tmp fix + d_new_result_next <= '0'; + when S_S_INIT => null; + when S_S_WRITE => + -- nur bei < 71 weiter machen + -- TODO: '/=' billiger als '<' ? + if unsigned(s_cnt_int) /= 71 then + wr_next <= '1'; + address_next <= std_logic_vector(unsigned(pos_int) + unsigned(s_cnt_int)); + data_in_next <= s_char; + s_cnt_next <= std_logic_vector(unsigned(s_cnt_int) + 1); + else + -- was_bs hier missbrauchen, um ein d_new_eingabe zu verhindern + was_bs_next <= '1'; + end if; + when S_S_BS => + -- ab 1 darf nicht mehr dekrementiert werden + addr_tmp := (others => '0'); + if unsigned(s_cnt_int) /= 1 then + addr_tmp(hspalte'length - 1 downto 0) := std_logic_vector(unsigned(s_cnt_int) - 1); + d_new_bs_next <= '1'; + else + addr_tmp(hspalte'length - 1 downto 0) := s_cnt_int; + end if; + s_cnt_next <= addr_tmp(hspalte'length - 1 downto 0); + + wr_next <= '1'; + address_next <= std_logic_vector(unsigned(pos_int) + unsigned(addr_tmp)); + data_in_next <= (others => '0'); + was_bs_next <= '1'; + when S_S_FIN => + finished_next <= '1'; + s_cnt_next <= (0 => '1', others => '0'); + d_new_result_next <= '1'; + when S_S_FIN_POSUP => + -- TODO: overflow nach 50 berechnungen... => wieder von vorne anfangen + pos_next <= std_logic_vector(unsigned(pos_int) + to_unsigned(142,H_RAM_WIDTH)); + when S_S_DONE => + s_done_next <= '1'; + if was_bs_int = '0' then + d_new_eingabe_next <= '1'; + end if; + if s_take = '0' then + was_bs_next <= '0'; + end if; + + when S_D_INIT => + addr_tmp := (others => '0'); + addr_tmp(hzeile'length - 1 downto 0) := d_zeile; + mul_tmp := std_logic_vector(unsigned(addr_tmp) * to_unsigned(71,H_RAM_WIDTH)); + addr_tmp := mul_tmp((addr_tmp'length - 1) downto 0); + addr_tmp := std_logic_vector(unsigned(addr_tmp) + unsigned(d_spalte)); + address_next <= addr_tmp; + d_new_eingabe_next <= '0'; + d_new_result_next <= '0'; + when S_D_READ => + d_char_next <= data_out; + d_done_next <= '1'; end case; end process; + + sp_ram_inst : entity work.sp_ram(beh) + generic map ( + ADDR_WIDTH => H_RAM_WIDTH + ) + port map ( + sys_clk => sys_clk, + address => address_int, + data_out => data_out, + wr => wr_int, + data_in => data_in_int + ); end architecture beh;