X-Git-Url: http://wien.tomnetworks.com/gitweb/?a=blobdiff_plain;f=src%2Fhistory.vhd;h=0c918687d73c07d569e9ef03b9cf7793042d9cf0;hb=51361c5dc1ab06332a04260f5192adcb398238e6;hp=ddd26f62b11fbc4233c8700c442cac2419d78c79;hpb=c4835e02b7f9b0d71547aec609667b7b5aed75ce;p=hwmod.git diff --git a/src/history.vhd b/src/history.vhd index ddd26f6..0c91868 100644 --- a/src/history.vhd +++ b/src/history.vhd @@ -13,7 +13,6 @@ entity history is pc_zeile : in hzeile; pc_char : out hbyte; pc_done : out std_logic; - pc_busy : out std_logic; -- Scanner s_char : in hbyte; s_take : in std_logic; @@ -42,7 +41,7 @@ end entity history; architecture beh of history is type HISTORY_STATE is (SIDLE, S_S_INIT, S_S_WRITE, S_S_BS, S_S_DONE, S_S_FIN, S_D_INIT, S_D_READ, S_S_FIN_POSUP, S_P_READ, S_P_READ_DONE, S_P_WRITE, - S_P_WRITE_DONE, S_P_DONE, S_INIT, S_S_CLEAR_NEXT0, S_S_CLEAR_NEXT1, S_PC_INIT, S_PC_DUMMY ,S_PC_READ); + S_P_WRITE_DONE, S_P_DONE, S_INIT, S_S_CLEAR_NEXT0, S_S_CLEAR_NEXT1, S_PC_INIT, S_PC_READ); signal state_int, state_next : HISTORY_STATE; signal was_bs_int, was_bs_next : std_logic; signal pos_int, pos_next : std_logic_vector(H_RAM_WIDTH - 1 downto 0); @@ -60,7 +59,6 @@ architecture beh of history is signal p_sp_write_int, p_sp_write_next : hspalte; signal pc_char_next ,pc_char_int : hbyte; signal pc_done_next, pc_done_int : std_logic; - signal pc_busy_next, pc_busy_int : std_logic; -- ram signal address_next, address_int : std_logic_vector(H_RAM_WIDTH - 1 downto 0); @@ -77,7 +75,6 @@ begin p_wdone <= p_wdone_int; p_read <= p_read_int; pc_done <= pc_done_int; - pc_busy <= pc_busy_int; pc_char <= pc_char_int; process(sys_clk, sys_res_n) @@ -99,11 +96,10 @@ begin p_wdone_int <= '0'; p_read_int <= (others => '0'); p_sp_read_int <= (others => '0'); - p_sp_write_int <= std_logic_vector(to_unsigned(71,p_sp_write_int'length)); + p_sp_write_int <= std_logic_vector(to_unsigned(HSPALTE_MAX,p_sp_write_int'length)); pc_char_int <= (others => '0'); pc_done_int <= '0'; - pc_busy_int <= '0'; address_int <= (0 => '1', others => '0'); data_in_int <= x"00"; @@ -129,7 +125,6 @@ begin pc_char_int <= pc_char_next; pc_done_int <= pc_done_next; - pc_busy_int <= pc_busy_next; address_int <= address_next; data_in_int <= data_in_next; @@ -182,11 +177,11 @@ begin when S_S_FIN_POSUP => state_next <= S_S_CLEAR_NEXT0; when S_S_CLEAR_NEXT0 => - if s_cnt_int = hspalte(to_unsigned(71,hspalte'length)) then + if s_cnt_int = hspalte(to_unsigned(HSPALTE_MAX,hspalte'length)) then state_next <= S_S_CLEAR_NEXT1; end if; when S_S_CLEAR_NEXT1 => - if s_cnt_int = hspalte(to_unsigned(71,hspalte'length)) then + if s_cnt_int = hspalte(to_unsigned(HSPALTE_MAX,hspalte'length)) then state_next <= SIDLE; end if; when S_S_DONE => @@ -201,8 +196,6 @@ begin state_next <= SIDLE; end if; when S_PC_INIT => - state_next <= S_PC_DUMMY; - when S_PC_DUMMY => state_next <= S_PC_READ; when S_PC_READ => if pc_get = '0' then @@ -248,7 +241,6 @@ begin data_in_next <= data_in_int; pc_done_next <= '0'; pc_char_next <= pc_char_int; - pc_busy_next <= '0'; p_rdone_next <= p_rdone_int; p_wdone_next <= p_wdone_int; p_read_next <= p_read_int; @@ -270,9 +262,9 @@ begin when S_S_INIT => null; when S_S_WRITE => - -- nur bei < 71 weiter machen + -- nur bei < HSPALTE_MAX weiter machen -- Hint: '/=' billiger als '<' - if unsigned(s_cnt_int) /= 71 then + if unsigned(s_cnt_int) /= HSPALTE_MAX then wr_next <= '1'; address_next <= std_logic_vector(unsigned(pos_int) + unsigned(s_cnt_int)); data_in_next <= s_char; @@ -300,7 +292,7 @@ begin d_new_result_next <= '1'; -- resetten der parser counter p_sp_read_next <= (others => '0'); - p_sp_write_next <= std_logic_vector(to_unsigned(71,p_sp_write_next'length)); + p_sp_write_next <= std_logic_vector(to_unsigned(HSPALTE_MAX,p_sp_write_next'length)); when S_S_FIN_POSUP => -- overflowcheck nach 50 berechnungen => wieder von vorne anfangen if pos_int = std_logic_vector(to_unsigned(H_RAM_SIZE-142,H_RAM_WIDTH)) then @@ -313,7 +305,7 @@ begin wr_next <= '1'; address_next <= std_logic_vector(unsigned(pos_int) + unsigned(s_cnt_int)); data_in_next <= (others => '0'); - if s_cnt_int = hspalte(to_unsigned(71,hspalte'length)) then + if s_cnt_int = hspalte(to_unsigned(HSPALTE_MAX,hspalte'length)) then s_cnt_next <= (0 => '1', others => '0'); else s_cnt_next <= std_logic_vector(unsigned(s_cnt_int) + 1); @@ -321,9 +313,9 @@ begin when S_S_CLEAR_NEXT1 => -- die naechsten 142 bytes im speicher resetten wr_next <= '1'; - address_next <= std_logic_vector(unsigned(pos_int) + to_unsigned(71,H_RAM_WIDTH) + unsigned(s_cnt_int)); + address_next <= std_logic_vector(unsigned(pos_int) + to_unsigned(HSPALTE_MAX,H_RAM_WIDTH) + unsigned(s_cnt_int)); data_in_next <= (others => '0'); - if s_cnt_int = hspalte(to_unsigned(71,hspalte'length)) then + if s_cnt_int = hspalte(to_unsigned(HSPALTE_MAX,hspalte'length)) then s_cnt_next <= (0 => '1', others => '0'); else s_cnt_next <= std_logic_vector(unsigned(s_cnt_int) + 1); @@ -340,7 +332,7 @@ begin when S_D_INIT => addr_tmp := (others => '0'); addr_tmp(hzeile'length - 1 downto 0) := d_zeile; - mul_tmp := std_logic_vector(unsigned(addr_tmp) * to_unsigned(71,H_RAM_WIDTH)); + mul_tmp := std_logic_vector(unsigned(addr_tmp) * to_unsigned(HSPALTE_MAX,H_RAM_WIDTH)); addr_tmp := mul_tmp((addr_tmp'length - 1) downto 0); addr_tmp := std_logic_vector(unsigned(addr_tmp) + unsigned(d_spalte)); address_next <= addr_tmp; @@ -353,16 +345,14 @@ begin when S_PC_INIT => addr_tmp := (others => '0'); addr_tmp(hzeile'length - 1 downto 0) := pc_zeile; - mul_tmp := std_logic_vector(unsigned(addr_tmp) * to_unsigned(71,H_RAM_WIDTH)); + mul_tmp := std_logic_vector(unsigned(addr_tmp) * to_unsigned(HSPALTE_MAX,H_RAM_WIDTH)); addr_tmp := mul_tmp((addr_tmp'length - 1) downto 0); addr_tmp := std_logic_vector(unsigned(addr_tmp) + unsigned(pc_spalte)); address_next <= addr_tmp; - pc_busy_next <= '1'; - when S_PC_DUMMY => - pc_busy_next <= '1'; when S_PC_READ => - pc_char_next <= data_out; pc_done_next <= '1'; + pc_char_next <= data_out; + when S_P_READ => wr_next <= '0'; spalte_tmp := std_logic_vector(unsigned(p_sp_read_int) + 1); @@ -377,7 +367,7 @@ begin data_in_next <= p_write; spalte_tmp := std_logic_vector(unsigned(p_sp_write_int) - 1); p_sp_write_next <= spalte_tmp; - address_next <= std_logic_vector(unsigned(pos_int) + to_unsigned(71,H_RAM_WIDTH) + unsigned(spalte_tmp)); + address_next <= std_logic_vector(unsigned(pos_int) + to_unsigned(HSPALTE_MAX,H_RAM_WIDTH) + unsigned(spalte_tmp)); when S_P_WRITE_DONE => p_wdone_next <= '1'; when S_P_DONE => @@ -386,7 +376,7 @@ begin end case; end process; - sp_ram_inst : entity work.sp_ram(beh) + sp_ram_inst : sp_ram generic map ( ADDR_WIDTH => H_RAM_WIDTH )