X-Git-Url: http://wien.tomnetworks.com/gitweb/?a=blobdiff_plain;f=src%2Fhistory.vhd;h=08b035904f5fae303825cae44c3214d7ed2fa9c4;hb=a2cb783f585122d43ebdab14a4d5d7e6d462366f;hp=c9f56569de863af75217b29fb36f012542daf21f;hpb=8f178b2ec0d1612a23da23b70baca1aaa7dade81;p=hwmod.git

diff --git a/src/history.vhd b/src/history.vhd
index c9f5656..08b0359 100644
--- a/src/history.vhd
+++ b/src/history.vhd
@@ -33,7 +33,7 @@ end entity history;
 
 architecture beh of history is
 	type HISTORY_STATE is (SIDLE, S_S_INIT, S_S_WRITE, S_S_BS, S_S_DONE, S_S_FIN,
-		S_D_INIT, S_D_WAIT, S_D_WRITE);
+		S_D_INIT, S_D_WRITE);
 	signal state_int, state_next : HISTORY_STATE;
 	signal s_done_int, s_done_next : std_logic;
 	signal s_cnt_int, s_cnt_next : hspalte;
@@ -102,12 +102,12 @@ begin
 		case state_int is
 			when SIDLE =>
 				-- S_S_FIN: tmp..
-				if d_get = '1' then
-					state_next <= S_D_INIT;
+				if s_take = '1' then
+					state_next <= S_S_INIT;
 				elsif do_it = '1' then
 					state_next <= S_S_FIN;
-				elsif s_take = '1' then
-					state_next <= S_S_INIT;
+				elsif d_get = '1' then
+					state_next <= S_D_INIT;
 				end if;
 			when S_S_INIT =>
 				if s_backspace = '1' then
@@ -127,8 +127,6 @@ begin
 				end if;
 
 			when S_D_INIT =>
-				state_next <= S_D_WAIT;
-			when S_D_WAIT =>
 				state_next <= S_D_WRITE;
 			when S_D_WRITE =>
 				if d_get = '0' then
@@ -153,18 +151,19 @@ begin
 		data_in_next <= data_in_int;
 
 		case state_int is
-			when SIDLE =>
-				null;
 			when S_S_INIT =>
 				null;
+			when SIDLE =>
+				-- TODO: tmp fix
+				d_new_result_next <= '0';
 			when S_S_WRITE =>
-				-- wr_next <= '1';
-				address_next <= '0' & s_cnt_int;
+				wr_next <= '1';
+				address_next <= s_cnt_int;
 				data_in_next <= s_char;
 				s_cnt_next <= std_logic_vector(unsigned(s_cnt_int) + 1);
 			when S_S_BS =>
-				-- wr_next <= '1';
-				address_next <= '0' & std_logic_vector(unsigned(s_cnt_int) - 1);
+				wr_next <= '1';
+				address_next <= std_logic_vector(unsigned(s_cnt_int) - 1);
 				data_in_next <= (others => '0');
 				if unsigned(s_cnt_int) /= 0 then
 					s_cnt_next <= std_logic_vector(unsigned(s_cnt_int) - 1);
@@ -178,11 +177,9 @@ begin
 				d_new_eingabe_next <= '1';
 
 			when S_D_INIT =>
-				address_next <= '0' & d_spalte;
+				address_next <= d_spalte;
 				d_new_eingabe_next <= '0';
 				d_new_result_next <= '0';
-			when S_D_WAIT =>
-				null;
 			when S_D_WRITE =>
 				d_char_next <= data_out;
 				d_done_next <= '1';