X-Git-Url: http://wien.tomnetworks.com/gitweb/?a=blobdiff_plain;f=src%2Fgen_pkg.vhd;h=f8a2963d90405aea55fe3bd4271915482288685a;hb=a1b9896ecd59e16ef6c28bc6990eadd6e0c515c8;hp=4dfbf6d9a738a2f0ac0d4ba9554087356665acdd;hpb=70a4a89db6d838884e39a4ed40a685c831db5d8a;p=hwmod.git diff --git a/src/gen_pkg.vhd b/src/gen_pkg.vhd index 4dfbf6d..f8a2963 100644 --- a/src/gen_pkg.vhd +++ b/src/gen_pkg.vhd @@ -18,107 +18,132 @@ package gen_pkg is -- integer ist 32bit (31bit + sign) subtype cinteger is integer; - -- 50 zeilen * 71 zeichen * 2 (berechnung + ergebnis) = 7100 bytes - constant H_RAM_SIZE : integer := 7100; - constant H_RAM_WIDTH : integer := log2c(H_RAM_SIZE); + + constant HSPALTE_MAX : integer := 71; subtype hspalte is std_logic_vector(6 downto 0); + + constant HZEILE_MAX : integer := 100; subtype hzeile is std_logic_vector(6 downto 0); + + -- 50 zeilen * 71 zeichen * 2 (berechnung + ergebnis) = 7100 bytes + constant H_RAM_SIZE : integer := HZEILE_MAX * HSPALTE_MAX; + constant H_RAM_WIDTH : integer := log2c(H_RAM_SIZE); + subtype hbyte is std_logic_vector(7 downto 0); - subtype hstring is string(1 to 72); - subtype hstr_int is integer range 0 to 72; + subtype hstring is string(1 to HSPALTE_MAX+1); + subtype hstr_int is integer range 0 to HSPALTE_MAX+1; - function find_msb(a : std_logic_vector) return std_logic_vector; procedure icwait(signal clk_i : IN std_logic; cycles: natural); + function ascii2sc (x : hbyte) return hbyte; + function valid_char (x : hbyte) return boolean; + function zeile2char(i : std_logic_vector; stelle : natural) return hbyte; + -- http://www.marjorie.de/ps2/scancode-set2.htm - constant SC_KP_0 : std_logic_vector(7 downto 0) := x"70"; - constant SC_KP_1 : std_logic_vector(7 downto 0) := x"69"; - constant SC_KP_2 : std_logic_vector(7 downto 0) := x"72"; - constant SC_KP_3 : std_logic_vector(7 downto 0) := x"7a"; - constant SC_KP_4 : std_logic_vector(7 downto 0) := x"6b"; - constant SC_KP_5 : std_logic_vector(7 downto 0) := x"73"; - constant SC_KP_6 : std_logic_vector(7 downto 0) := x"74"; - constant SC_KP_7 : std_logic_vector(7 downto 0) := x"6c"; - constant SC_KP_8 : std_logic_vector(7 downto 0) := x"75"; - constant SC_KP_9 : std_logic_vector(7 downto 0) := x"7d"; - - constant SC_0 : std_logic_vector(7 downto 0) := x"45"; - constant SC_1 : std_logic_vector(7 downto 0) := x"16"; - constant SC_2 : std_logic_vector(7 downto 0) := x"1e"; - constant SC_3 : std_logic_vector(7 downto 0) := x"26"; - constant SC_4 : std_logic_vector(7 downto 0) := x"25"; - constant SC_5 : std_logic_vector(7 downto 0) := x"2e"; - constant SC_6 : std_logic_vector(7 downto 0) := x"36"; - constant SC_7 : std_logic_vector(7 downto 0) := x"3d"; - constant SC_8 : std_logic_vector(7 downto 0) := x"3e"; - constant SC_9 : std_logic_vector(7 downto 0) := x"46"; - - constant SC_KP_PLUS : std_logic_vector(7 downto 0) := x"79"; - constant SC_KP_MINUS : std_logic_vector(7 downto 0) := x"7b"; - constant SC_KP_MUL : std_logic_vector(7 downto 0) := x"7c"; - constant SC_KP_DIV : std_logic_vector(7 downto 0) := x"4a"; -- inkl. 0xe0! + constant SC_KP_0 : hbyte := x"70"; + constant SC_KP_1 : hbyte := x"69"; + constant SC_KP_2 : hbyte := x"72"; + constant SC_KP_3 : hbyte := x"7a"; + constant SC_KP_4 : hbyte := x"6b"; + constant SC_KP_5 : hbyte := x"73"; + constant SC_KP_6 : hbyte := x"74"; + constant SC_KP_7 : hbyte := x"6c"; + constant SC_KP_8 : hbyte := x"75"; + constant SC_KP_9 : hbyte := x"7d"; + + constant SC_0 : hbyte := x"45"; + constant SC_1 : hbyte := x"16"; + constant SC_2 : hbyte := x"1e"; + constant SC_3 : hbyte := x"26"; + constant SC_4 : hbyte := x"25"; + constant SC_5 : hbyte := x"2e"; + constant SC_6 : hbyte := x"36"; + constant SC_7 : hbyte := x"3d"; + constant SC_8 : hbyte := x"3e"; + constant SC_9 : hbyte := x"46"; + + constant SC_KP_PLUS : hbyte := x"79"; + constant SC_KP_MINUS : hbyte := x"7b"; + constant SC_KP_MUL : hbyte := x"7c"; + constant SC_KP_DIV : hbyte := x"4a"; -- inkl. 0xe0! -- fuer deutsches layout, alle anderen zeichen sind unguenstig belegt - constant SC_PLUS : std_logic_vector(7 downto 0) := x"5b"; + constant SC_PLUS : hbyte := x"5b"; - constant SC_ENTER : std_logic_vector(7 downto 0) := x"5a"; - constant SC_BKSP : std_logic_vector(7 downto 0) := x"66"; - constant SC_SPACE : std_logic_vector(7 downto 0) := x"29"; + constant SC_ENTER : hbyte := x"5a"; + constant SC_BKSP : hbyte := x"66"; + constant SC_SPACE : hbyte := x"29"; end package gen_pkg; package body gen_pkg is - -- http://www.velocityreviews.com/forums/showpost.php?p=137148&postcount=5 - function find_msb(a : std_logic_vector) return std_logic_vector is - function bits_to_fit(n : positive) return natural is - variable nn, bits : natural := 0; - begin - nn := n; - while nn > 0 loop - bits := bits + 1; - nn := nn/2; - end loop; - return bits; - end; - - function or_all(p : std_logic_vector) return std_logic is - variable r : std_logic; - begin - r := '0'; - for i in p'range loop - r := r or p(i); - end loop; - return r; - end; - - constant wN : positive := bits_to_fit(a'length - 1); - constant wP : positive := 2 ** wN; - variable pv : std_logic_vector(wP-1 downto 0); - variable n : std_logic_vector(wN downto 1); - begin - if a'length <= 2 then - n(n'right) := a(a'left); - else - pv(a'length-1 downto 0) := a; - if or_all(pv(wP-1 downto wP/2)) = '1' then - n := '1' & find_msb((pv(wP-1 downto wP/2))); - else - n := '0' & find_msb((pv(wP/2-1 downto 0))); - end if; - end if; - return n; - end function find_msb; - -- -- alternativ: eleganter, braucht aber mehr logic cells - -- for i in (CBITS-1) downto 0 loop - -- exit when a(i) = '1'; - -- r := r+1; - -- end loop; - -- return (CBITS - r); - procedure icwait(signal clk_i : IN std_logic; cycles: Natural) is begin for i in 1 to cycles loop wait until clk_i= '0' and clk_i'event; end loop; end; -end package body gen_pkg; + function ascii2sc (x : hbyte) return hbyte is + variable y : hbyte; + begin + case x is + when x"30" => y := SC_KP_0; + when x"31" => y := SC_KP_1; + when x"32" => y := SC_KP_2; + when x"33" => y := SC_KP_3; + when x"34" => y := SC_KP_4; + when x"35" => y := SC_KP_5; + when x"36" => y := SC_KP_6; + when x"37" => y := SC_KP_7; + when x"38" => y := SC_KP_8; + when x"39" => y := SC_KP_9; + when x"2b" => y := SC_KP_PLUS; + when x"2d" => y := SC_KP_MINUS; + when x"2a" => y := SC_KP_MUL; + when x"2f" => y := SC_KP_DIV; + when x"20" => y := SC_SPACE; + when x"1c" => y := SC_ENTER; + when x"0e" => y := SC_BKSP; + when others => y := x"41"; + end case; + return y; + end function; + + function valid_char (x : hbyte) return boolean is + variable y : boolean; + begin + case x is + when SC_KP_0 | SC_KP_1 | SC_KP_2 | SC_KP_3 | + SC_KP_4 | SC_KP_5 | SC_KP_6 | SC_KP_7 | + SC_KP_8 | SC_KP_9 | SC_KP_PLUS | + SC_KP_MINUS | SC_KP_MUL | + SC_KP_DIV | SC_SPACE | + SC_BKSP | SC_ENTER => + y := true; + when others => y := false; + end case; + return y; + end function; + + function zeile2char(i : std_logic_vector; stelle : natural) return hbyte is + subtype zeilnum is string(1 to 2); + type zeilnum_arr is array (natural range 0 to 49) of zeilnum; + constant zn : zeilnum_arr := ( + 0 => "00", 1 => "01", 2 => "02", 3 => "03", 4 => "04", + 5 => "05", 6 => "06", 7 => "07", 8 => "08", 9 => "09", + 10 => "10", 11 => "11", 12 => "12", 13 => "13", 14 => "14", + 15 => "15", 16 => "16", 17 => "17", 18 => "18", 19 => "19", + 20 => "20", 21 => "21", 22 => "22", 23 => "23", 24 => "24", + 25 => "25", 26 => "26", 27 => "27", 28 => "28", 29 => "29", + 30 => "30", 31 => "31", 32 => "32", 33 => "33", 34 => "34", + 35 => "35", 36 => "36", 37 => "37", 38 => "38", 39 => "39", + 40 => "40", 41 => "41", 42 => "42", 43 => "43", 44 => "44", + 45 => "45", 46 => "46", 47 => "47", 48 => "48", 49 => "49", + others => "xy"); + variable t : signed(hzeile'length downto 0); + begin + t := signed('0' & i); + t := t / 2; + return hbyte(to_unsigned(character'pos(zn(to_integer(t))(stelle)),8)); + end; +end package body gen_pkg;