X-Git-Url: http://wien.tomnetworks.com/gitweb/?a=blobdiff_plain;f=src%2Fgen_pkg.vhd;h=c990f1b2f5354aa2c4670a9bcfbf53d310eb41ae;hb=09b4e91e343349c7c4c3b0e06fd4e2b79b8d95e6;hp=7f5e2dc30b387cbc02456b7276f66ac4fa648bd0;hpb=05882ef8805341c413d6f4748766fc01bcd2b3f7;p=hwmod.git

diff --git a/src/gen_pkg.vhd b/src/gen_pkg.vhd
index 7f5e2dc..c990f1b 100644
--- a/src/gen_pkg.vhd
+++ b/src/gen_pkg.vhd
@@ -1,6 +1,7 @@
 library ieee;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;
+use work.math_pkg.all;
 
 package gen_pkg is
 	subtype alu_ops is std_logic_vector(2 downto 0);
@@ -13,28 +14,91 @@ package gen_pkg is
 
 	constant CBITS : integer := 32;
 	subtype csigned is signed((CBITS-1) downto 0);
+	subtype divinteger is unsigned(4 downto 0);
 	-- integer ist 32bit (31bit + sign)
 	subtype cinteger is integer;
 
+	-- 50 zeilen * 71 zeichen * 2 (berechnung + ergebnis) = 7100 bytes
+	constant H_RAM_SIZE : integer := 7100;
+	constant H_RAM_WIDTH : integer := log2c(H_RAM_SIZE);
 	subtype hspalte is std_logic_vector(6 downto 0);
-	subtype hzeile is std_logic_vector(4 downto 0);
+	subtype hzeile is std_logic_vector(6 downto 0);
 	subtype hbyte is std_logic_vector(7 downto 0);
-	subtype hstring is string(1 to 71);
+	subtype hstring is string(1 to 72);
+	subtype hstr_int is integer range 0 to 72;
 
-	function find_msb(a : csigned) return natural;
-	procedure icwait(signal clk_i : IN std_logic; cycles: Natural);
+	function find_msb(a : std_logic_vector) return std_logic_vector;
+	procedure icwait(signal clk_i : IN std_logic; cycles: natural);
+
+	-- http://www.marjorie.de/ps2/scancode-set2.htm
+	constant SC_KP_0 : std_logic_vector(7 downto 0) := x"70";
+	constant SC_KP_1 : std_logic_vector(7 downto 0) := x"69";
+	constant SC_KP_2 : std_logic_vector(7 downto 0) := x"72";
+	constant SC_KP_3 : std_logic_vector(7 downto 0) := x"7a";
+	constant SC_KP_4 : std_logic_vector(7 downto 0) := x"6b";
+	constant SC_KP_5 : std_logic_vector(7 downto 0) := x"73";
+	constant SC_KP_6 : std_logic_vector(7 downto 0) := x"74";
+	constant SC_KP_7 : std_logic_vector(7 downto 0) := x"6c";
+	constant SC_KP_8 : std_logic_vector(7 downto 0) := x"75";
+	constant SC_KP_9 : std_logic_vector(7 downto 0) := x"7d";
+
+	constant SC_KP_PLUS : std_logic_vector(7 downto 0) := x"79";
+	constant SC_KP_MINUS : std_logic_vector(7 downto 0) := x"7b";
+	constant SC_KP_MUL : std_logic_vector(7 downto 0) := x"7c";
+	constant SC_KP_DIV : std_logic_vector(7 downto 0) := x"4a"; -- inkl. 0xe0!
+
+	constant SC_ENTER : std_logic_vector(7 downto 0) := x"5a";
+	constant SC_BKSP : std_logic_vector(7 downto 0) := x"66";
+	constant SC_SPACE : std_logic_vector(7 downto 0) := x"29";
 end package gen_pkg;
 
 package body gen_pkg is
-	function find_msb(a : csigned) return natural is
-		variable r : natural := 0;
+	-- http://www.velocityreviews.com/forums/showpost.php?p=137148&postcount=5
+	function find_msb(a : std_logic_vector) return std_logic_vector is
+		function bits_to_fit(n : positive) return natural is
+			variable nn, bits : natural := 0;
+		begin
+			nn := n;
+			while nn > 0 loop
+				bits := bits + 1;
+				nn := nn/2;
+			end loop;
+			return bits;
+		end;
+
+		function or_all(p : std_logic_vector) return std_logic is
+			variable r : std_logic;
+		begin
+			r := '0';
+			for i in p'range loop
+				r := r or p(i);
+			end loop;
+			return r;
+		end;
+
+		constant wN : positive := bits_to_fit(a'length - 1);
+		constant wP : positive := 2 ** wN;
+		variable pv : std_logic_vector(wP-1 downto 0);
+		variable n : std_logic_vector(wN downto 1);
 	begin
-		for i in (CBITS-1) downto 0 loop
-			exit when a(i) = '1';
-			r := r+1;
-		end loop;
-		return (CBITS - r);
+		if a'length <= 2 then
+			n(n'right) := a(a'left);
+		else
+			pv(a'length-1 downto 0) := a;
+			if or_all(pv(wP-1 downto wP/2)) = '1' then
+				n := '1' & find_msb((pv(wP-1 downto wP/2)));
+			else
+				n := '0' & find_msb((pv(wP/2-1 downto 0)));
+			end if;
+		end if;
+		return n;
 	end function find_msb;
+	-- -- alternativ: eleganter, braucht aber mehr logic cells
+	-- for i in (CBITS-1) downto 0 loop
+	--       exit when a(i) = '1';
+	--       r := r+1;
+	-- end loop;
+	-- return (CBITS - r);
 
 	procedure icwait(signal clk_i : IN std_logic; cycles: Natural) is
 	begin