X-Git-Url: http://wien.tomnetworks.com/gitweb/?a=blobdiff_plain;f=src%2Fgen_pkg.vhd;h=6b2e92e42c3f777b2687a088a2b79bea6afac9fa;hb=78b81af08fdecb68941b50aa298dc6b8492ce770;hp=dfe664c1fb05b077a27ef2e4ae84de0cf9bb117c;hpb=b42b2b9d669e1d12db43c70704b4657901d1ab02;p=hwmod.git diff --git a/src/gen_pkg.vhd b/src/gen_pkg.vhd index dfe664c..6b2e92e 100644 --- a/src/gen_pkg.vhd +++ b/src/gen_pkg.vhd @@ -37,6 +37,7 @@ package gen_pkg is function ascii2sc (x : hbyte) return hbyte; function valid_char (x : hbyte) return boolean; + function zeile2char(i : std_logic_vector; stelle : natural) return hbyte; -- http://www.marjorie.de/ps2/scancode-set2.htm constant SC_KP_0 : hbyte := x"70"; @@ -72,6 +73,191 @@ package gen_pkg is constant SC_ENTER : hbyte := x"5a"; constant SC_BKSP : hbyte := x"66"; constant SC_SPACE : hbyte := x"29"; + + -- components... + component alu is + port ( + sys_clk : in std_logic; + sys_res_n : in std_logic; + opcode : in alu_ops; + op1 : in csigned; + op2 : in csigned; + op3 : out csigned; + opM : out csigned; + do_calc : in std_logic; + calc_done : out std_logic; + calc_error : out std_logic + ); + end component alu; + + component parser is + port ( + sys_clk : in std_logic; + sys_res_n : in std_logic; + -- History + p_rget : out std_logic; + p_rdone : in std_logic; + p_read : in hbyte; + p_wtake : out std_logic; + p_wdone : in std_logic; + p_write : out hbyte; + p_finished : out std_logic; + -- Scanner + do_it : in std_logic; + finished : out std_logic + ); + end component parser; + + component scanner is + port ( + sys_clk : in std_logic; + sys_res_n : in std_logic; + -- PS/2 + new_data : in std_logic; + data : in std_logic_vector(7 downto 0); + -- History + s_char : out hbyte; + s_take : out std_logic; + s_done : in std_logic; + s_backspace : out std_logic; + -- Parser + do_it : out std_logic; + finished : in std_logic + ); + end component scanner; + + component history is + port ( + sys_clk : in std_logic; + sys_res_n : in std_logic; + -- PC-komm + pc_get : in std_logic; + pc_spalte : in hspalte; + pc_zeile : in hzeile; + pc_char : out hbyte; + pc_done : out std_logic; + -- Scanner + s_char : in hbyte; + s_take : in std_logic; + s_done : out std_logic; + s_backspace : in std_logic; + -- Display + d_new_eingabe : out std_logic; + d_new_result : out std_logic; + d_new_bs : out std_logic; + d_zeile : in hzeile; + d_spalte : in hspalte; + d_get : in std_logic; + d_done : out std_logic; + d_char : out hbyte; + -- Parser + p_rget : in std_logic; + p_rdone : out std_logic; + p_read : out hbyte; + p_wtake : in std_logic; + p_wdone : out std_logic; + p_write : in hbyte; + p_finished : in std_logic + ); + end component history; + + component display is + port ( + sys_clk : in std_logic; + sys_res_n : in std_logic; + -- History + d_new_eingabe : in std_logic; + d_new_result : in std_logic; + d_new_bs : in std_logic; + d_zeile : out hzeile; + d_spalte : out hspalte; + d_get : out std_logic; + d_done : in std_logic; + d_char : in hbyte; + -- VGA + command : out std_logic_vector(7 downto 0); + command_data : out std_logic_vector(31 downto 0); + free : in std_logic + ); + end component display; + + component pc_communication is + port ( + sys_clk : in std_logic; + sys_res_n : in std_logic; + --button + btn_a : in std_logic; + --uart_tx + tx_data : out std_logic_vector(7 downto 0); + tx_new : out std_logic; + tx_done : in std_logic; + --uart_rx + rx_data : in std_logic_vector(7 downto 0); + rx_new : in std_logic; + -- History + pc_zeile : out hzeile; + pc_spalte : out hspalte; + pc_get : out std_logic; + pc_done : in std_logic; + pc_char : in hbyte + ); + end component pc_communication; + + component uart_rx is + generic ( + CLK_FREQ : integer := 33000000; + BAUDRATE : integer := 115200 + ); + port( + sys_clk : in std_logic; + sys_res_n : in std_logic; + rxd : in std_logic; + rx_data : out std_logic_vector(7 downto 0); + rx_new : out std_logic + ); + end component uart_rx; + + component uart_tx is + generic ( + CLK_FREQ : integer := 33000000; + BAUDRATE : integer := 115200 + ); + port( + sys_clk : in std_logic; + sys_res_n : in std_logic; + txd : out std_logic; + tx_data : in std_logic_vector(7 downto 0); + tx_new : in std_logic; + tx_done : out std_logic + ); + end component uart_tx; + + component vpll IS + port ( + inclk0 : in std_logic := '0'; + c0 : out std_logic + ); + end component vpll; + + component clk_vga_s3e is + port ( + clk50 : in std_logic; + clk25 : out std_logic + ); + end component clk_vga_s3e; + + component sp_ram is + generic ( + ADDR_WIDTH : integer range 1 to integer'high + ); + port ( + sys_clk : in std_logic; + address : in std_logic_vector(ADDR_WIDTH - 1 downto 0); + data_out : out hbyte; + wr : in std_logic; + data_in : in hbyte + ); + end component sp_ram; end package gen_pkg; package body gen_pkg is @@ -123,4 +309,26 @@ package body gen_pkg is end case; return y; end function; + + function zeile2char(i : std_logic_vector; stelle : natural) return hbyte is + subtype zeilnum is string(1 to 2); + type zeilnum_arr is array (natural range 0 to 49) of zeilnum; + constant zn : zeilnum_arr := ( + 0 => "00", 1 => "01", 2 => "02", 3 => "03", 4 => "04", + 5 => "05", 6 => "06", 7 => "07", 8 => "08", 9 => "09", + 10 => "10", 11 => "11", 12 => "12", 13 => "13", 14 => "14", + 15 => "15", 16 => "16", 17 => "17", 18 => "18", 19 => "19", + 20 => "20", 21 => "21", 22 => "22", 23 => "23", 24 => "24", + 25 => "25", 26 => "26", 27 => "27", 28 => "28", 29 => "29", + 30 => "30", 31 => "31", 32 => "32", 33 => "33", 34 => "34", + 35 => "35", 36 => "36", 37 => "37", 38 => "38", 39 => "39", + 40 => "40", 41 => "41", 42 => "42", 43 => "43", 44 => "44", + 45 => "45", 46 => "46", 47 => "47", 48 => "48", 49 => "49", + others => "xy"); + variable t : signed(hzeile'length downto 0); + begin + t := signed('0' & i); + t := t / 2; + return hbyte(to_unsigned(character'pos(zn(to_integer(t))(stelle)),8)); + end; end package body gen_pkg;