X-Git-Url: http://wien.tomnetworks.com/gitweb/?a=blobdiff_plain;f=src%2Fcpu%2Fx86%2Fsmm%2Fsmihandler.c;h=7d6dfe41004273a27abfb0982f9b9161d621bafa;hb=c35a4511f715b926852117d30ac106c4709fba26;hp=1ea9e1926e470f34900abb4cdbdd38f118192afe;hpb=edf480719a69912c39f4a1d31f50898eb3982c5b;p=coreboot.git

diff --git a/src/cpu/x86/smm/smihandler.c b/src/cpu/x86/smm/smihandler.c
index 1ea9e1926..7d6dfe410 100644
--- a/src/cpu/x86/smm/smihandler.c
+++ b/src/cpu/x86/smm/smihandler.c
@@ -1,7 +1,7 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright (C) 2008 coresystems GmbH
+ * Copyright (C) 2008-2009 coresystems GmbH
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License as
@@ -27,7 +27,7 @@
 
 void southbridge_smi_set_eos(void);
 
-#define DEBUG_SMI
+/* To enable SMI define DEBUG_SMI in smiutil.c */
 
 typedef enum { SMI_LOCKED, SMI_UNLOCKED } smi_semaphore;
 
@@ -67,66 +67,6 @@ static inline __attribute__((always_inline)) unsigned long nodeid(void)
 	return (*((volatile unsigned long *)(LAPIC_ID)) >> 24);
 }
 
-/* ********************* smi_util ************************* */
-
-/* Data */
-#define UART_RBR 0x00
-#define UART_TBR 0x00
-
-/* Control */
-#define UART_IER 0x01
-#define UART_IIR 0x02
-#define UART_FCR 0x02
-#define UART_LCR 0x03
-#define UART_MCR 0x04
-#define UART_DLL 0x00
-#define UART_DLM 0x01
-
-/* Status */
-#define UART_LSR 0x05
-#define UART_MSR 0x06
-#define UART_SCR 0x07
-
-static int uart_can_tx_byte(void)
-{
-	return inb(TTYS0_BASE + UART_LSR) & 0x20;
-}
-
-static void uart_wait_to_tx_byte(void)
-{
-	while(!uart_can_tx_byte()) 
-	;
-}
-
-static void uart_wait_until_sent(void)
-{
-	while(!(inb(TTYS0_BASE + UART_LSR) & 0x40))
-	; 
-}
-
-static void uart_tx_byte(unsigned char data)
-{
-	uart_wait_to_tx_byte();
-	outb(data, TTYS0_BASE + UART_TBR);
-	/* Make certain the data clears the fifos */
-	uart_wait_until_sent();
-}
-
-void console_tx_flush(void)
-{
-	uart_wait_to_tx_byte();
-}
-
-void console_tx_byte(unsigned char byte)
-{
-	if (byte == '\n')
-		uart_tx_byte('\r');
-	uart_tx_byte(byte);
-}
-
-/* ********************* smi_util ************************* */
-
-
 void io_trap_handler(int smif)
 {
 	/* If a handler function handled a given IO trap, it
@@ -163,18 +103,19 @@ void smi_handler(u32 smm_revision)
 	smm_state_save_area_t state_save;
 
 	/* Are we ok to execute the handler? */
-	if (!smi_obtain_lock())
+	if (!smi_obtain_lock()) {
+		/* For security reasons we don't release the other CPUs
+		 * until the CPU with the lock is actually done
+		 */
+		while (smi_handler_status == SMI_LOCKED) /* wait */ ;
 		return;
+	}
 
 	node=nodeid();
 
-#ifdef DEBUG_SMI
-	console_loglevel = DEFAULT_CONSOLE_LOGLEVEL;
-#else
-	console_loglevel = 1;
-#endif
+	console_init();
 
-	printk_debug("\nSMI# #%d\n", node);
+	printk_spew("\nSMI# #%d\n", node);
 
 	switch (smm_revision) {
 	case 0x00030007:
@@ -201,6 +142,10 @@ void smi_handler(u32 smm_revision)
 		return;
 	}
 
+	/* Call chipset specific SMI handlers. This would be the place to
+	 * add a CPU or northbridge specific SMI handler, too
+	 */
+
 	southbridge_smi_handler(node, &state_save);
 
 	smi_release_lock();