X-Git-Url: http://wien.tomnetworks.com/gitweb/?a=blobdiff_plain;f=src%2Fcpu%2Fx86%2Flapic%2Flapic_cpu_init.c;h=fc22ea4adf9a9e7fd5b8996475f485b518a283b6;hb=5ff7c13e858a31addf1558731a12cf6c753b576d;hp=3033902525d9c0c26f778a38602b5c30ecd59c4e;hpb=9d24c7f202c4ff353a8a97e955ee68ed340a98b1;p=coreboot.git

diff --git a/src/cpu/x86/lapic/lapic_cpu_init.c b/src/cpu/x86/lapic/lapic_cpu_init.c
index 303390252..fc22ea4ad 100644
--- a/src/cpu/x86/lapic/lapic_cpu_init.c
+++ b/src/cpu/x86/lapic/lapic_cpu_init.c
@@ -16,8 +16,6 @@
 #include <cpu/cpu.h>
 
 #if CONFIG_SMP == 1
-
-#if CONFIG_RAMBASE >= 0x100000
 /* This is a lot more paranoid now, since Linux can NOT handle
  * being told there is a CPU when none exists. So any errors
  * will return 0, meaning no CPU.
@@ -29,7 +27,6 @@ static unsigned long get_valid_start_eip(unsigned long orig_start_eip)
 {
 	return (unsigned long)orig_start_eip & 0xffff; // 16 bit to avoid 0xa0000
 }
-#endif
 
 #if CONFIG_HAVE_ACPI_RESUME == 1
 char *lowmem_backup;
@@ -41,7 +38,6 @@ extern char _secondary_start[];
 
 static void copy_secondary_start_to_1m_below(void)
 {
-#if CONFIG_RAMBASE >= 0x100000
 	extern char _secondary_start_end[];
 	unsigned long code_size;
 	unsigned long start_eip;
@@ -66,8 +62,7 @@ static void copy_secondary_start_to_1m_below(void)
 	/* copy the _secondary_start to the ram below 1M*/
 	memcpy((unsigned char *)start_eip, (unsigned char *)_secondary_start, code_size);
 
-	printk_debug("start_eip=0x%08lx, offset=0x%08lx, code_size=0x%08lx\n", start_eip, ((unsigned long)_secondary_start - start_eip), code_size);
-#endif
+	printk(BIOS_DEBUG, "start_eip=0x%08lx, offset=0x%08lx, code_size=0x%08lx\n", start_eip, ((unsigned long)_secondary_start - start_eip), code_size);
 }
 
 static int lapic_start_cpu(unsigned long apicid)
@@ -80,7 +75,7 @@ static int lapic_start_cpu(unsigned long apicid)
 	 * Starting actual IPI sequence...
 	 */
 
-	printk_spew("Asserting INIT.\n");
+	printk(BIOS_SPEW, "Asserting INIT.\n");
 
 	/*
 	 * Turn INIT on target chip
@@ -94,28 +89,30 @@ static int lapic_start_cpu(unsigned long apicid)
 	lapic_write_around(LAPIC_ICR, LAPIC_INT_LEVELTRIG | LAPIC_INT_ASSERT
 				| LAPIC_DM_INIT);
 
-	printk_spew("Waiting for send to finish...\n");
+	printk(BIOS_SPEW, "Waiting for send to finish...\n");
 	timeout = 0;
 	do {
-		printk_spew("+");
+		printk(BIOS_SPEW, "+");
 		udelay(100);
 		send_status = lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY;
 	} while (send_status && (timeout++ < 1000));
 	if (timeout >= 1000) {
-		printk_err("CPU %ld: First apic write timed out. Disabling\n",
+		printk(BIOS_ERR, "CPU %ld: First apic write timed out. Disabling\n",
 			 apicid);
 		// too bad.
-		printk_err("ESR is 0x%lx\n", lapic_read(LAPIC_ESR));
+		printk(BIOS_ERR, "ESR is 0x%lx\n", lapic_read(LAPIC_ESR));
 		if (lapic_read(LAPIC_ESR)) {
-			printk_err("Try to reset ESR\n");
+			printk(BIOS_ERR, "Try to reset ESR\n");
 			lapic_write_around(LAPIC_ESR, 0);
-			printk_err("ESR is 0x%lx\n", lapic_read(LAPIC_ESR));
+			printk(BIOS_ERR, "ESR is 0x%lx\n", lapic_read(LAPIC_ESR));
 		}
 		return 0;
 	}
+#if !defined (CONFIG_CPU_AMD_MODEL_10XXX) && !defined (CONFIG_CPU_AMD_MODEL_14XXX)
 	mdelay(10);
+#endif
 
-	printk_spew("Deasserting INIT.\n");
+	printk(BIOS_SPEW, "Deasserting INIT.\n");
 
 	/* Target chip */
 	lapic_write_around(LAPIC_ICR2, SET_LAPIC_DEST_FIELD(apicid));
@@ -123,41 +120,41 @@ static int lapic_start_cpu(unsigned long apicid)
 	/* Send IPI */
 	lapic_write_around(LAPIC_ICR, LAPIC_INT_LEVELTRIG | LAPIC_DM_INIT);
 
-	printk_spew("Waiting for send to finish...\n");
+	printk(BIOS_SPEW, "Waiting for send to finish...\n");
 	timeout = 0;
 	do {
-		printk_spew("+");
+		printk(BIOS_SPEW, "+");
 		udelay(100);
 		send_status = lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY;
 	} while (send_status && (timeout++ < 1000));
 	if (timeout >= 1000) {
-		printk_err("CPU %ld: Second apic write timed out. Disabling\n",
+		printk(BIOS_ERR, "CPU %ld: Second apic write timed out. Disabling\n",
 			 apicid);
 		// too bad.
 		return 0;
 	}
 
-#if CONFIG_RAMBASE >= 0x100000
 	start_eip = get_valid_start_eip((unsigned long)_secondary_start);
-#else
-	start_eip = (unsigned long)_secondary_start;
-#endif
 
+#if !defined (CONFIG_CPU_AMD_MODEL_10XXX) && !defined (CONFIG_CPU_AMD_MODEL_14XXX)
 	num_starts = 2;
+#else
+	num_starts = 1;
+#endif
 
 	/*
 	 * Run STARTUP IPI loop.
 	 */
-	printk_spew("#startup loops: %d.\n", num_starts);
+	printk(BIOS_SPEW, "#startup loops: %d.\n", num_starts);
 
 	maxlvt = 4;
 
 	for (j = 1; j <= num_starts; j++) {
-		printk_spew("Sending STARTUP #%d to %lu.\n", j, apicid);
+		printk(BIOS_SPEW, "Sending STARTUP #%d to %lu.\n", j, apicid);
 		lapic_read_around(LAPIC_SPIV);
 		lapic_write(LAPIC_ESR, 0);
 		lapic_read(LAPIC_ESR);
-		printk_spew("After apic_write.\n");
+		printk(BIOS_SPEW, "After apic_write.\n");
 
 		/*
 		 * STARTUP IPI
@@ -176,12 +173,12 @@ static int lapic_start_cpu(unsigned long apicid)
 		 */
 		udelay(300);
 
-		printk_spew("Startup point 1.\n");
+		printk(BIOS_SPEW, "Startup point 1.\n");
 
-		printk_spew("Waiting for send to finish...\n");
+		printk(BIOS_SPEW, "Waiting for send to finish...\n");
 		timeout = 0;
 		do {
-			printk_spew("+");
+			printk(BIOS_SPEW, "+");
 			udelay(100);
 			send_status = lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY;
 		} while (send_status && (timeout++ < 1000));
@@ -201,11 +198,11 @@ static int lapic_start_cpu(unsigned long apicid)
 		if (send_status || accept_status)
 			break;
 	}
-	printk_spew("After Startup.\n");
+	printk(BIOS_SPEW, "After Startup.\n");
 	if (send_status)
-		printk_warning("APIC never delivered???\n");
+		printk(BIOS_WARNING, "APIC never delivered???\n");
 	if (accept_status)
-		printk_warning("APIC delivery error (%lx).\n", accept_status);
+		printk(BIOS_WARNING, "APIC delivery error (%lx).\n", accept_status);
 	if (send_status || accept_status)
 		return 0;
 	return 1;
@@ -265,7 +262,7 @@ int start_cpu(device_t cpu)
 
 	if (result) {
 		result = 0;
-		/* Wait 1s or until the new the new cpu calls in */
+		/* Wait 1s or until the new cpu calls in */
 		for(count = 0; count < 100000 ; count++) {
 			if (secondary_stack == 0) {
 				result = 1;
@@ -294,7 +291,7 @@ void stop_this_cpu(void)
 
 	id = lapic_read(LAPIC_ID) >> 24;
 
-	printk_debug("CPU %ld going down...\n", id);
+	printk(BIOS_DEBUG, "CPU %ld going down...\n", id);
 
 	/* send an LAPIC INIT to myself */
 	lapic_write_around(LAPIC_ICR2, SET_LAPIC_DEST_FIELD(id));
@@ -302,37 +299,37 @@ void stop_this_cpu(void)
 
 	/* wait for the ipi send to finish */
 #if 0
-	// When these two printk_spew calls are not removed, the
+	// When these two printk(BIOS_SPEW, ...) calls are not removed, the
 	// machine will hang when log level is SPEW. Why?
-	printk_spew("Waiting for send to finish...\n");
+	printk(BIOS_SPEW, "Waiting for send to finish...\n");
 #endif
 	timeout = 0;
 	do {
 #if 0
-		printk_spew("+");
+		printk(BIOS_SPEW, "+");
 #endif
 		udelay(100);
 		send_status = lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY;
 	} while (send_status && (timeout++ < 1000));
 	if (timeout >= 1000) {
-		printk_err("timed out\n");
+		printk(BIOS_ERR, "timed out\n");
 	}
 	mdelay(10);
 
-	printk_spew("Deasserting INIT.\n");
+	printk(BIOS_SPEW, "Deasserting INIT.\n");
 	/* Deassert the LAPIC INIT */
 	lapic_write_around(LAPIC_ICR2, SET_LAPIC_DEST_FIELD(id));
 	lapic_write_around(LAPIC_ICR, LAPIC_INT_LEVELTRIG | LAPIC_DM_INIT);
 
-	printk_spew("Waiting for send to finish...\n");
+	printk(BIOS_SPEW, "Waiting for send to finish...\n");
 	timeout = 0;
 	do {
-		printk_spew("+");
+		printk(BIOS_SPEW, "+");
 		udelay(100);
 		send_status = lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY;
 	} while (send_status && (timeout++ < 1000));
 	if (timeout >= 1000) {
-		printk_err("timed out\n");
+		printk(BIOS_ERR, "timed out\n");
 	}
 
 	while(1) {
@@ -341,6 +338,26 @@ void stop_this_cpu(void)
 }
 #endif
 
+#ifdef __SSE3__
+static __inline__ __attribute__((always_inline)) unsigned long readcr4(void)
+{
+	unsigned long value;
+	__asm__ __volatile__ (
+			"mov %%cr4, %[value]"
+			: [value] "=a" (value));
+	return value;
+}
+
+static __inline__ __attribute__((always_inline)) void writecr4(unsigned long Data)
+{
+	__asm__ __volatile__ (
+			"mov %%eax, %%cr4"
+			:
+			: "a" (Data)
+			);
+}
+#endif
+
 /* C entry point of secondary cpus */
 void secondary_cpu_init(void)
 {
@@ -350,6 +367,17 @@ void secondary_cpu_init(void)
 	spin_lock(&start_cpu_lock);
   #endif
 #endif
+
+#ifdef __SSE3__
+	/*
+	 * Seems that CR4 was cleared when AP start via lapic_start_cpu()
+	 * Turn on CR4.OSFXSR and CR4.OSXMMEXCPT when SSE options enabled
+	 */
+	u32 cr4_val;
+	cr4_val = readcr4();
+	cr4_val |= (1 << 9 | 1 << 10);
+	writecr4(cr4_val);
+#endif
 	cpu_initialize();
 #if CONFIG_SERIAL_CPU_INIT == 1
   #if CONFIG_MAX_CPUS>2
@@ -387,7 +415,7 @@ static void start_other_cpus(struct bus *cpu_bus, device_t bsp_cpu)
 
 		if (!start_cpu(cpu)) {
 			/* Record the error in cpu? */
-			printk_err("CPU 0x%02x would not start!\n",
+			printk(BIOS_ERR, "CPU 0x%02x would not start!\n",
 				cpu->path.apic.apic_id);
 		}
 #if CONFIG_SERIAL_CPU_INIT == 1
@@ -408,7 +436,7 @@ static void wait_other_cpus_stop(struct bus *cpu_bus)
 	active_count = atomic_read(&active_cpus);
 	while(active_count > 1) {
 		if (active_count != old_active_count) {
-			printk_info("Waiting for %d CPUS to stop\n", active_count - 1);
+			printk(BIOS_INFO, "Waiting for %d CPUS to stop\n", active_count - 1);
 			old_active_count = active_count;
 		}
 		udelay(10);
@@ -419,11 +447,11 @@ static void wait_other_cpus_stop(struct bus *cpu_bus)
 			continue;
 		}
 		if (!cpu->initialized) {
-			printk_err("CPU 0x%02x did not initialize!\n",
+			printk(BIOS_ERR, "CPU 0x%02x did not initialize!\n",
 				cpu->path.apic.apic_id);
 		}
 	}
-	printk_debug("All AP CPUs stopped\n");
+	printk(BIOS_DEBUG, "All AP CPUs stopped\n");
 }
 
 #else /* CONFIG_SMP */