X-Git-Url: http://wien.tomnetworks.com/gitweb/?a=blobdiff_plain;f=src%2Fcpu%2Fx86%2Flapic%2Flapic_cpu_init.c;h=ed9940c4acf1b2c78145dee7b88a3ae79f08b3b3;hb=67aa3d6b878c5deea8d14054cce700ac1d045505;hp=4a879c561a67a4236ab1d65ea0fb4ab86e9b7c33;hpb=c4ddbff70621449606fa3f0a1ad8277fac0f5aeb;p=coreboot.git diff --git a/src/cpu/x86/lapic/lapic_cpu_init.c b/src/cpu/x86/lapic/lapic_cpu_init.c index 4a879c561..ed9940c4a 100644 --- a/src/cpu/x86/lapic/lapic_cpu_init.c +++ b/src/cpu/x86/lapic/lapic_cpu_init.c @@ -1,6 +1,6 @@ /* 2005.12 yhlu add coreboot_ram cross the vga font buffer handling - 2005.12 yhlu add _RAMBASE above 1M support for SMP + 2005.12 yhlu add CONFIG_RAMBASE above 1M support for SMP 2008.05 stepan add support for going back to sipi wait state */ @@ -16,40 +16,53 @@ #include #if CONFIG_SMP == 1 - -#if _RAMBASE >= 0x100000 /* This is a lot more paranoid now, since Linux can NOT handle - * being told there is a CPU when none exists. So any errors - * will return 0, meaning no CPU. + * being told there is a CPU when none exists. So any errors + * will return 0, meaning no CPU. * * We actually handling that case by noting which cpus startup * and not telling anyone about the ones that dont. - */ + */ static unsigned long get_valid_start_eip(unsigned long orig_start_eip) { - return (unsigned long)orig_start_eip & 0xffff; // 16 bit to avoid 0xa0000 + return (unsigned long)orig_start_eip & 0xffff; // 16 bit to avoid 0xa0000 } + +#if CONFIG_HAVE_ACPI_RESUME == 1 +char *lowmem_backup; +char *lowmem_backup_ptr; +int lowmem_backup_size; #endif -static void copy_secondary_start_to_1m_below(void) +extern char _secondary_start[]; + +static void copy_secondary_start_to_1m_below(void) { -#if _RAMBASE >= 0x100000 - extern char _secondary_start[]; - extern char _secondary_start_end[]; - unsigned long code_size; - unsigned long start_eip; - - /* _secondary_start need to be masked 20 above bit, because 16 bit code in secondary.S - Also We need to copy the _secondary_start to the below 1M region - */ - start_eip = get_valid_start_eip((unsigned long)_secondary_start); - code_size = (unsigned long)_secondary_start_end - (unsigned long)_secondary_start; - - /* copy the _secondary_start to the ram below 1M*/ - memcpy((unsigned char *)start_eip, (unsigned char *)_secondary_start, code_size); - - printk_debug("start_eip=0x%08lx, offset=0x%08lx, code_size=0x%08lx\n", start_eip, ((unsigned long)_secondary_start - start_eip), code_size); + extern char _secondary_start_end[]; + unsigned long code_size; + unsigned long start_eip; + + /* _secondary_start need to be masked 20 above bit, because 16 bit code in secondary.S + Also We need to copy the _secondary_start to the below 1M region + */ + start_eip = get_valid_start_eip((unsigned long)_secondary_start); + code_size = (unsigned long)_secondary_start_end - (unsigned long)_secondary_start; + +#if CONFIG_HAVE_ACPI_RESUME == 1 + /* need to save it for RAM resume */ + lowmem_backup_size = code_size; + lowmem_backup = malloc(code_size); + lowmem_backup_ptr = (char *)start_eip; + + if (lowmem_backup == NULL) + die("Out of backup memory\n"); + + memcpy(lowmem_backup, lowmem_backup_ptr, lowmem_backup_size); #endif + /* copy the _secondary_start to the ram below 1M*/ + memcpy((unsigned char *)start_eip, (unsigned char *)_secondary_start, code_size); + + printk(BIOS_DEBUG, "start_eip=0x%08lx, offset=0x%08lx, code_size=0x%08lx\n", start_eip, ((unsigned long)_secondary_start - start_eip), code_size); } static int lapic_start_cpu(unsigned long apicid) @@ -57,13 +70,12 @@ static int lapic_start_cpu(unsigned long apicid) int timeout; unsigned long send_status, accept_status, start_eip; int j, num_starts, maxlvt; - extern char _secondary_start[]; - + /* * Starting actual IPI sequence... */ - printk_spew("Asserting INIT.\n"); + printk(BIOS_SPEW, "Asserting INIT.\n"); /* * Turn INIT on target chip @@ -73,74 +85,76 @@ static int lapic_start_cpu(unsigned long apicid) /* * Send IPI */ - + lapic_write_around(LAPIC_ICR, LAPIC_INT_LEVELTRIG | LAPIC_INT_ASSERT | LAPIC_DM_INIT); - printk_spew("Waiting for send to finish...\n"); + printk(BIOS_SPEW, "Waiting for send to finish...\n"); timeout = 0; do { - printk_spew("+"); + printk(BIOS_SPEW, "+"); udelay(100); send_status = lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY; } while (send_status && (timeout++ < 1000)); if (timeout >= 1000) { - printk_err("CPU %ld: First apic write timed out. Disabling\n", + printk(BIOS_ERR, "CPU %ld: First apic write timed out. Disabling\n", apicid); - // too bad. - printk_err("ESR is 0x%lx\n", lapic_read(LAPIC_ESR)); + // too bad. + printk(BIOS_ERR, "ESR is 0x%lx\n", lapic_read(LAPIC_ESR)); if (lapic_read(LAPIC_ESR)) { - printk_err("Try to reset ESR\n"); + printk(BIOS_ERR, "Try to reset ESR\n"); lapic_write_around(LAPIC_ESR, 0); - printk_err("ESR is 0x%lx\n", lapic_read(LAPIC_ESR)); + printk(BIOS_ERR, "ESR is 0x%lx\n", lapic_read(LAPIC_ESR)); } return 0; } +#if !defined (CONFIG_CPU_AMD_MODEL_10XXX) && !defined (CONFIG_CPU_AMD_MODEL_14XXX) mdelay(10); +#endif - printk_spew("Deasserting INIT.\n"); + printk(BIOS_SPEW, "Deasserting INIT.\n"); /* Target chip */ lapic_write_around(LAPIC_ICR2, SET_LAPIC_DEST_FIELD(apicid)); /* Send IPI */ lapic_write_around(LAPIC_ICR, LAPIC_INT_LEVELTRIG | LAPIC_DM_INIT); - - printk_spew("Waiting for send to finish...\n"); + + printk(BIOS_SPEW, "Waiting for send to finish...\n"); timeout = 0; do { - printk_spew("+"); + printk(BIOS_SPEW, "+"); udelay(100); send_status = lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY; } while (send_status && (timeout++ < 1000)); if (timeout >= 1000) { - printk_err("CPU %ld: Second apic write timed out. Disabling\n", + printk(BIOS_ERR, "CPU %ld: Second apic write timed out. Disabling\n", apicid); - // too bad. + // too bad. return 0; } -#if _RAMBASE >= 0x100000 start_eip = get_valid_start_eip((unsigned long)_secondary_start); -#else - start_eip = (unsigned long)_secondary_start; -#endif +#if !defined (CONFIG_CPU_AMD_MODEL_10XXX) && !defined (CONFIG_CPU_AMD_MODEL_14XXX) num_starts = 2; +#else + num_starts = 1; +#endif /* * Run STARTUP IPI loop. */ - printk_spew("#startup loops: %d.\n", num_starts); + printk(BIOS_SPEW, "#startup loops: %d.\n", num_starts); maxlvt = 4; for (j = 1; j <= num_starts; j++) { - printk_spew("Sending STARTUP #%d to %u.\n", j, apicid); + printk(BIOS_SPEW, "Sending STARTUP #%d to %lu.\n", j, apicid); lapic_read_around(LAPIC_SPIV); lapic_write(LAPIC_ESR, 0); lapic_read(LAPIC_ESR); - printk_spew("After apic_write.\n"); + printk(BIOS_SPEW, "After apic_write.\n"); /* * STARTUP IPI @@ -159,12 +173,12 @@ static int lapic_start_cpu(unsigned long apicid) */ udelay(300); - printk_spew("Startup point 1.\n"); + printk(BIOS_SPEW, "Startup point 1.\n"); - printk_spew("Waiting for send to finish...\n"); + printk(BIOS_SPEW, "Waiting for send to finish...\n"); timeout = 0; do { - printk_spew("+"); + printk(BIOS_SPEW, "+"); udelay(100); send_status = lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY; } while (send_status && (timeout++ < 1000)); @@ -184,11 +198,11 @@ static int lapic_start_cpu(unsigned long apicid) if (send_status || accept_status) break; } - printk_spew("After Startup.\n"); + printk(BIOS_SPEW, "After Startup.\n"); if (send_status) - printk_warning("APIC never delivered???\n"); + printk(BIOS_WARNING, "APIC never delivered???\n"); if (accept_status) - printk_warning("APIC delivery error (%lx).\n", accept_status); + printk(BIOS_WARNING, "APIC delivery error (%lx).\n", accept_status); if (send_status || accept_status) return 0; return 1; @@ -223,32 +237,14 @@ int start_cpu(device_t cpu) spin_lock(&start_cpu_lock); /* Get the cpu's apicid */ - apicid = cpu->path.u.apic.apic_id; + apicid = cpu->path.apic.apic_id; /* Get an index for the new processor */ index = ++last_cpu_index; - + /* Find end of the new processors stack */ -#if (CONFIG_LB_MEM_TOPK>1024) && (_RAMBASE < 0x100000) && ((CONFIG_CONSOLE_VGA==1) || (CONFIG_PCI_ROM_RUN == 1)) - if(index<1) { // only keep bsp on low - stack_end = ((unsigned long)_estack) - (STACK_SIZE*index) - sizeof(struct cpu_info); - } else { - // for all APs, let use stack after pgtbl, 20480 is the pgtbl size for every cpu - stack_end = 0x100000+(20480 + STACK_SIZE)*CONFIG_MAX_CPUS - (STACK_SIZE*index); -#if (0x100000+(20480 + STACK_SIZE)*CONFIG_MAX_CPU) > (CONFIG_LB_MEM_TOPK<<10) - #warning "We may need to increase CONFIG_LB_MEM_TOPK, it need to be more than (0x100000+(20480 + STACK_SIZE)*CONFIG_MAX_CPU)\n" -#endif - if(stack_end > (CONFIG_LB_MEM_TOPK<<10)) { - printk_debug("start_cpu: Please increase the CONFIG_LB_MEM_TOPK more than %dK\n", stack_end>>10); - die("Can not go on\n"); - } - stack_end -= sizeof(struct cpu_info); - } -#else - stack_end = ((unsigned long)_estack) - (STACK_SIZE*index) - sizeof(struct cpu_info); -#endif + stack_end = ((unsigned long)_estack) - (CONFIG_STACK_SIZE*index) - sizeof(struct cpu_info); - /* Record the index and which cpu structure we are using */ info = (struct cpu_info *)stack_end; info->index = index; @@ -266,7 +262,7 @@ int start_cpu(device_t cpu) if (result) { result = 0; - /* Wait 1s or until the new the new cpu calls in */ + /* Wait 1s or until the new cpu calls in */ for(count = 0; count < 100000 ; count++) { if (secondary_stack == 0) { result = 1; @@ -281,6 +277,19 @@ int start_cpu(device_t cpu) } #if CONFIG_AP_IN_SIPI_WAIT == 1 + +/** + * Sending INIT IPI to self is equivalent of asserting #INIT with a bit of delay. + * An undefined number of instruction cycles will complete. All global locks + * must be released before INIT IPI and no printk is allowed after this. + * De-asserting INIT IPI is a no-op on later Intel CPUs. + * + * If you set DEBUG_HALT_SELF to 1, printk's after INIT IPI are enabled + * but running thread may halt without releasing the lock and effectively + * deadlock other CPUs. + */ +#define DEBUG_HALT_SELF 0 + /** * Normally this function is defined in lapic.h as an always inline function * that just keeps the CPU in a hlt() loop. This does not work on all CPUs. @@ -291,49 +300,57 @@ void stop_this_cpu(void) { int timeout; unsigned long send_status; - unsigned long lapicid; + unsigned long id; - lapicid = lapic_read(LAPIC_ID) >> 24; + id = lapic_read(LAPIC_ID) >> 24; - printk_debug("CPU %d going down...\n", lapicid); + printk(BIOS_DEBUG, "CPU %ld going down...\n", id); /* send an LAPIC INIT to myself */ - lapic_write_around(LAPIC_ICR2, SET_LAPIC_DEST_FIELD(lapicid)); + lapic_write_around(LAPIC_ICR2, SET_LAPIC_DEST_FIELD(id)); lapic_write_around(LAPIC_ICR, LAPIC_INT_LEVELTRIG | LAPIC_INT_ASSERT | LAPIC_DM_INIT); /* wait for the ipi send to finish */ -#if 0 - // When these two printk_spew calls are not removed, the - // machine will hang when log level is SPEW. Why? - printk_spew("Waiting for send to finish...\n"); +#if DEBUG_HALT_SELF + printk(BIOS_SPEW, "Waiting for send to finish...\n"); #endif timeout = 0; do { -#if 0 - printk_spew("+"); +#if DEBUG_HALT_SELF + printk(BIOS_SPEW, "+"); #endif udelay(100); send_status = lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY; } while (send_status && (timeout++ < 1000)); if (timeout >= 1000) { - printk_err("timed out\n"); +#if DEBUG_HALT_SELF + printk(BIOS_ERR, "timed out\n"); +#endif } mdelay(10); - printk_spew("Deasserting INIT.\n"); +#if DEBUG_HALT_SELF + printk(BIOS_SPEW, "Deasserting INIT.\n"); +#endif /* Deassert the LAPIC INIT */ - lapic_write_around(LAPIC_ICR2, SET_LAPIC_DEST_FIELD(lapicid)); + lapic_write_around(LAPIC_ICR2, SET_LAPIC_DEST_FIELD(id)); lapic_write_around(LAPIC_ICR, LAPIC_INT_LEVELTRIG | LAPIC_DM_INIT); - printk_spew("Waiting for send to finish...\n"); +#if DEBUG_HALT_SELF + printk(BIOS_SPEW, "Waiting for send to finish...\n"); +#endif timeout = 0; do { - printk_spew("+"); +#if DEBUG_HALT_SELF + printk(BIOS_SPEW, "+"); +#endif udelay(100); send_status = lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY; } while (send_status && (timeout++ < 1000)); if (timeout >= 1000) { - printk_err("timed out\n"); +#if DEBUG_HALT_SELF + printk(BIOS_ERR, "timed out\n"); +#endif } while(1) { @@ -342,20 +359,47 @@ void stop_this_cpu(void) } #endif +#ifdef __SSE3__ +static __inline__ __attribute__((always_inline)) unsigned long readcr4(void) +{ + unsigned long value; + __asm__ __volatile__ ( + "mov %%cr4, %[value]" + : [value] "=a" (value)); + return value; +} + +static __inline__ __attribute__((always_inline)) void writecr4(unsigned long Data) +{ + __asm__ __volatile__ ( + "mov %%eax, %%cr4" + : + : "a" (Data) + ); +} +#endif + /* C entry point of secondary cpus */ void secondary_cpu_init(void) { atomic_inc(&active_cpus); -#if SERIAL_CPU_INIT == 1 - #if CONFIG_MAX_CPUS>2 +#if CONFIG_SERIAL_CPU_INIT == 1 spin_lock(&start_cpu_lock); - #endif +#endif + +#ifdef __SSE3__ + /* + * Seems that CR4 was cleared when AP start via lapic_start_cpu() + * Turn on CR4.OSFXSR and CR4.OSXMMEXCPT when SSE options enabled + */ + u32 cr4_val; + cr4_val = readcr4(); + cr4_val |= (1 << 9 | 1 << 10); + writecr4(cr4_val); #endif cpu_initialize(); -#if SERIAL_CPU_INIT == 1 - #if CONFIG_MAX_CPUS>2 +#if CONFIG_SERIAL_CPU_INIT == 1 spin_unlock(&start_cpu_lock); - #endif #endif atomic_dec(&active_cpus); @@ -372,9 +416,9 @@ static void start_other_cpus(struct bus *cpu_bus, device_t bsp_cpu) if (cpu->path.type != DEVICE_PATH_APIC) { continue; } - #if SERIAL_CPU_INIT == 0 + #if CONFIG_SERIAL_CPU_INIT == 0 if(cpu==bsp_cpu) { - continue; + continue; } #endif @@ -388,13 +432,11 @@ static void start_other_cpus(struct bus *cpu_bus, device_t bsp_cpu) if (!start_cpu(cpu)) { /* Record the error in cpu? */ - printk_err("CPU 0x%02x would not start!\n", - cpu->path.u.apic.apic_id); + printk(BIOS_ERR, "CPU 0x%02x would not start!\n", + cpu->path.apic.apic_id); } -#if SERIAL_CPU_INIT == 1 - #if CONFIG_MAX_CPUS>2 +#if CONFIG_SERIAL_CPU_INIT == 1 udelay(10); - #endif #endif } @@ -409,7 +451,7 @@ static void wait_other_cpus_stop(struct bus *cpu_bus) active_count = atomic_read(&active_cpus); while(active_count > 1) { if (active_count != old_active_count) { - printk_info("Waiting for %d CPUS to stop\n", active_count - 1); + printk(BIOS_INFO, "Waiting for %d CPUS to stop\n", active_count - 1); old_active_count = active_count; } udelay(10); @@ -420,27 +462,17 @@ static void wait_other_cpus_stop(struct bus *cpu_bus) continue; } if (!cpu->initialized) { - printk_err("CPU 0x%02x did not initialize!\n", - cpu->path.u.apic.apic_id); + printk(BIOS_ERR, "CPU 0x%02x did not initialize!\n", + cpu->path.apic.apic_id); } } - printk_debug("All AP CPUs stopped\n"); + printk(BIOS_DEBUG, "All AP CPUs stopped\n"); } #else /* CONFIG_SMP */ #define initialize_other_cpus(root) do {} while(0) #endif /* CONFIG_SMP */ -#if WAIT_BEFORE_CPUS_INIT==0 - #define cpus_ready_for_init() do {} while(0) -#else - void cpus_ready_for_init(void); -#endif - -#if HAVE_SMI_HANDLER -void smm_init(void); -#endif - void initialize_cpus(struct bus *cpu_bus) { struct device_path cpu_path; @@ -455,11 +487,11 @@ void initialize_cpus(struct bus *cpu_bus) /* Get the device path of the boot cpu */ cpu_path.type = DEVICE_PATH_APIC; - cpu_path.u.apic.apic_id = lapicid(); + cpu_path.apic.apic_id = lapicid(); #else /* Get the device path of the boot cpu */ cpu_path.type = DEVICE_PATH_CPU; - cpu_path.u.cpu.id = 0; + cpu_path.cpu.id = 0; #endif /* Find the device structure for the boot cpu */ @@ -469,26 +501,26 @@ void initialize_cpus(struct bus *cpu_bus) copy_secondary_start_to_1m_below(); // why here? In case some day we can start core1 in amd_sibling_init #endif -#if HAVE_SMI_HANDLER +#if CONFIG_HAVE_SMI_HANDLER smm_init(); #endif - cpus_ready_for_init(); + cpus_ready_for_init(); #if CONFIG_SMP == 1 - #if SERIAL_CPU_INIT == 0 + #if CONFIG_SERIAL_CPU_INIT == 0 /* start all aps at first, so we can init ECC all together */ - start_other_cpus(cpu_bus, info->cpu); + start_other_cpus(cpu_bus, info->cpu); #endif #endif - /* Initialize the bootstrap processor */ - cpu_initialize(); + /* Initialize the bootstrap processor */ + cpu_initialize(); #if CONFIG_SMP == 1 - #if SERIAL_CPU_INIT == 1 - start_other_cpus(cpu_bus, info->cpu); - #endif + #if CONFIG_SERIAL_CPU_INIT == 1 + start_other_cpus(cpu_bus, info->cpu); + #endif /* Now wait the rest of the cpus stop*/ wait_other_cpus_stop(cpu_bus);