X-Git-Url: http://wien.tomnetworks.com/gitweb/?a=blobdiff_plain;f=src%2Fcpu%2Fintel%2Fmodel_6ex%2Fmodel_6ex_init.c;h=384b2bf68b8b9107cdcf88ead6e179c63f10c2d0;hb=554c052b48ac0b36503cb41b1c054a5ead7ae4b4;hp=6ecaca6d15242288c7ca1c79614999f850ea50e5;hpb=45cc550c3ab24e6c68fd0f9dd5ea2f96cf9afc38;p=coreboot.git diff --git a/src/cpu/intel/model_6ex/model_6ex_init.c b/src/cpu/intel/model_6ex/model_6ex_init.c index 6ecaca6d1..384b2bf68 100644 --- a/src/cpu/intel/model_6ex/model_6ex_init.c +++ b/src/cpu/intel/model_6ex/model_6ex_init.c @@ -1,3 +1,24 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + #include #include #include @@ -9,10 +30,13 @@ #include #include #include -#include +#include +#include static const uint32_t microcode_updates[] = { - #include "microcode_m206e839.h" + #include "microcode-1624-m206e839.h" + #include "microcode-1729-m206ec54.h" + #include "microcode-1869-m806ec59.h" /* Dummy terminator */ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, @@ -20,38 +44,6 @@ static const uint32_t microcode_updates[] = { 0x0, 0x0, 0x0, 0x0, }; -static inline void strcpy(char *dst, char *src) -{ - while (*src) *dst++ = *src++; -} - -static void fill_processor_name(char *processor_name) -{ - struct cpuid_result regs; - char temp_processor_name[49]; - char *processor_name_start; - unsigned int *name_as_ints = (unsigned int *)temp_processor_name; - int i; - - for (i=0; i<3; i++) { - regs = cpuid(0x80000002 + i); - name_as_ints[i*4 + 0] = regs.eax; - name_as_ints[i*4 + 1] = regs.ebx; - name_as_ints[i*4 + 2] = regs.ecx; - name_as_ints[i*4 + 3] = regs.edx; - } - - temp_processor_name[48] = 0; - - /* Skip leading spaces */ - processor_name_start = temp_processor_name; - while (*processor_name_start == ' ') - processor_name_start++; - - memset(processor_name, 0, 49); - strcpy(processor_name, processor_name_start); -} - #define IA32_FEATURE_CONTROL 0x003a #define CPUID_VMX (1 << 5) @@ -85,15 +77,44 @@ static void enable_vmx(void) } #define PMG_CST_CONFIG_CONTROL 0xe2 +#define PMG_IO_BASE_ADDR 0xe3 +#define PMG_IO_CAPTURE_ADDR 0xe4 + +/* MWAIT coordination I/O base address. This must match + * the \_PR_.CPU0 PM base address. + */ +#define PMB0_BASE 0x510 + +/* PMB1: I/O port that triggers SMI once cores are in the same state. + * See CSM Trigger, at PMG_CST_CONFIG_CONTROL[6:4] + */ +#define PMB1_BASE 0x800 +#define HIGHEST_CLEVEL 3 static void configure_c_states(void) { msr_t msr; msr = rdmsr(PMG_CST_CONFIG_CONTROL); - msr.lo &= ~(1 << 9); // Issue a single stop grant cycle upon stpclk - + msr.lo |= (1 << 15); // config lock until next reset. + msr.lo |= (1 << 10); // Enable I/O MWAIT redirection for C-States + msr.lo &= ~(1 << 9); // Issue a single stop grant cycle upon stpclk // TODO Do we want Deep C4 and Dynamic L2 shrinking? + + /* Number of supported C-States */ + msr.lo &= ~7; + msr.lo |= HIGHEST_CLEVEL; // support at most C3 + wrmsr(PMG_CST_CONFIG_CONTROL, msr); + + /* Set Processor MWAIT IO BASE (P_BLK) */ + msr.hi = 0; + msr.lo = ((PMB0_BASE + 4) & 0xffff) | (((PMB1_BASE + 9) & 0xffff) << 16); + wrmsr(PMG_IO_BASE_ADDR, msr); + + /* set C_LVL controls */ + msr.hi = 0; + msr.lo = (PMB0_BASE + 4) | ((HIGHEST_CLEVEL - 2) << 16); // -2 because LVL0+1 aren't counted + wrmsr(PMG_IO_CAPTURE_ADDR, msr); } #define IA32_MISC_ENABLE 0x1a0 @@ -118,7 +139,20 @@ static void configure_misc(void) wrmsr(IA32_MISC_ENABLE, msr); } -#if CONFIG_USBDEBUG_DIRECT +#define PIC_SENS_CFG 0x1aa +static void configure_pic_thermal_sensors(void) +{ + msr_t msr; + + msr = rdmsr(PIC_SENS_CFG); + + msr.lo |= (1 << 21); // inter-core lock TM1 + msr.lo |= (1 << 4); // Enable bypass filter + + wrmsr(PIC_SENS_CFG, msr); +} + +#if CONFIG_USBDEBUG static unsigned ehci_debug_addr; #endif @@ -134,11 +168,11 @@ static void model_6ex_init(device_t cpu) /* Print processor name */ fill_processor_name(processor_name); - printk_info("CPU: %s.\n", processor_name); + printk(BIOS_INFO, "CPU: %s.\n", processor_name); -#if CONFIG_USBDEBUG_DIRECT +#if CONFIG_USBDEBUG // Is this caution really needed? - if(!ehci_debug_addr) + if(!ehci_debug_addr) ehci_debug_addr = get_ehci_debug(); set_ehci_debug(0); #endif @@ -147,7 +181,7 @@ static void model_6ex_init(device_t cpu) x86_setup_mtrrs(36); x86_mtrr_check(); -#if CONFIG_USBDEBUG_DIRECT +#if CONFIG_USBDEBUG set_ehci_debug(ehci_debug_addr); #endif @@ -163,7 +197,8 @@ static void model_6ex_init(device_t cpu) /* Configure Enhanced SpeedStep and Thermal Sensors */ configure_misc(); - /* TODO: PIC thermal sensor control */ + /* PIC thermal sensor control */ + configure_pic_thermal_sensors(); /* Start up my cpu siblings */ intel_sibling_init(cpu); @@ -176,6 +211,7 @@ static struct device_operations cpu_dev_ops = { static struct cpu_device_id cpu_table[] = { { X86_VENDOR_INTEL, 0x06e0 }, /* Intel Core Solo/Core Duo */ { X86_VENDOR_INTEL, 0x06e8 }, /* Intel Core Solo/Core Duo */ + { X86_VENDOR_INTEL, 0x06ec }, /* Intel Core Solo/Core Duo */ { 0, 0 }, };