X-Git-Url: http://wien.tomnetworks.com/gitweb/?a=blobdiff_plain;f=src%2Fcpu%2Famd%2Fmodel_gx2%2Fcpubug.c;h=ccc9dbec160b1cff81772466205630e2e940f79c;hb=9d0b30dd2b33d04859986be85b125c3005b2a277;hp=3c512089384451e5f396c9317d2aa2001f859a1f;hpb=d8d8fffa0edc8b86f1efab2f3a44c9d53cefe556;p=coreboot.git

diff --git a/src/cpu/amd/model_gx2/cpubug.c b/src/cpu/amd/model_gx2/cpubug.c
index 3c5120893..ccc9dbec1 100644
--- a/src/cpu/amd/model_gx2/cpubug.c
+++ b/src/cpu/amd/model_gx2/cpubug.c
@@ -31,25 +31,46 @@ bug573(void){
 }
 #endif
 
+/**************************************************************************
+ *
+ *	pcideadlock
+ *
+ *	Bugtool #465 and #609
+ *	PCI cache deadlock
+ *	There is also fix code in cache and PCI functions. This bug is very is pervasive.
+ *
+ *	Entry:
+ *	Exit:
+ *	Modified:
+ *
+ **************************************************************************/
 static void
 pcideadlock(void)
 {
 	msr_t msr;
 
+	/*
+	 * forces serialization of all load misses. Setting this bit prevents the 
+	 * DM pipe from backing up if a read request has to be held up waiting 
+	 * for PCI writes to complete.
+	*/
 	msr = rdmsr(CPU_DM_CONFIG0);
 	msr.hi &= ~(7<<DM_CONFIG0_UPPER_WSREQ_SHIFT);
 	msr.hi |= (2<<DM_CONFIG0_UPPER_WSREQ_SHIFT);
 	msr.lo |= DM_CONFIG0_LOWER_MISSER_SET;
 	wrmsr(CPU_DM_CONFIG0, msr);
 
+	/* interlock instruction fetches to WS regions with data accesses.
+	 * This prevents an instruction fetch from going out to PCI if the 
+	 * data side is about to make a request.
+	 */
 	msr = rdmsr(CPU_IM_CONFIG);
-	msr.lo |= IM_CONFIG_LOWER_QWT_SET;	/* interlock instruction fetches to WS regions with data accesses.
-						 * This prevents in instruction fetch from going out to PCI if the 
-						 * data side is about to make a request.
-						 */
+	msr.lo |= IM_CONFIG_LOWER_QWT_SET;
 	wrmsr(CPU_IM_CONFIG, msr);
-	/* write serialize memory hole to PCI. Need to to unWS when something is shadowed regardless of cachablility.*/
-
+	
+	/* write serialize memory hole to PCI. Need to unWS when something is 
+	 * shadowed regardless of cachablility.
+	 */
 	msr.lo = 0x021212121;
 	msr.hi = 0x021212121;
 	wrmsr( CPU_RCONF_A0_BF, msr);
@@ -57,19 +78,19 @@ pcideadlock(void)
 	wrmsr( CPU_RCONF_E0_FF, msr);
 }
 
-/****************************************************************************/
-/***/
-/**	CPUbug784*/
-/***/
-/**	Bugtool #784 + #792*/
-/***/
-/**	Fix CPUID instructions for < 3.0 CPUs*/
-/***/
-/**	Entry:*/
-/**	Exit:*/
-/**	Modified:*/
-/***/
-/****************************************************************************/
+/**************************************************************************** 
+ *
+ *	CPUbug784
+ *
+ *	Bugtool #784 + #792
+ *
+ *	Fix CPUID instructions for < 3.0 CPUs
+ *
+ *	Entry:
+ *	Exit:
+ *	Modified:
+ *
+ ****************************************************************************/
 
 void bug784(void)
 {
@@ -99,134 +120,132 @@ void bug784(void)
 }
 
 /* cpubug 1398: enable MC if we KNOW we have DDR*/
+/**************************************************************************
+ *
+ *	CPUbugIAENG1398
+ *
+ *	ClearQuest #IAENG1398
+ *	The MC can not be enabled with SDR memory but can for DDR. Enable for
+ *	DDR here if the setup token is "Default"
+ *	Add this back to core by default once 2.0 CPUs are not supported.
+ *	Entry:
+ *	Exit:
+ *	Modified:
+ *
+ **************************************************************************/
 void eng1398(void)
 {
 	msr_t msr;
 
 	msr = rdmsr(MSR_GLCP+0x17);
-	if ((msr.lo & 0xff) < CPU_REV_2_0) {
+	if ((msr.lo & 0xff) <= CPU_REV_2_0) {
 		msr = rdmsr(GLCP_SYS_RSTPLL);
 		if (msr.lo & (1<<RSTPPL_LOWER_SDRMODE_SHIFT))
 			return;
 	}
 
-	/* no bios to check, we just go for it? */
+	/* no CMOS/NVRAM to check, so enable MC Clock Gating */
 	msr = rdmsr(MC_GLD_MSR_PM);
 	msr.lo |= 3; /* enable MC clock gating.*/
 	wrmsr(MC_GLD_MSR_PM, msr);
 }
 
+/***************************************************************************
+ *
+ *	CPUbugIAENG2900
+ *
+ *	Clear Quest IAENG00002900, VSS 118.150
+ *
+ *	BTB issue causes blue screen in windows, but the fix is required
+ *	for all operating systems.
+ *
+ *	Entry:
+ *	Exit:
+ *	Modified:
+ *
+ **************************************************************************/
 void
-eng2900(void){
-	printk_err(" NOT DOING eng2900: only shown to be a windows problem\n");
-#if 0
+eng2900(void)
+{
+	msr_t msr;
 
-;**************************************************************************
-;*
-;*	CPUbugIAENG2900
-;*
-;*	Clear Quest IAENG00002900, VSS 118.150
-;*
-;*	BTB issue causes blue screen in windows.
-;*
-;*	Entry:
-;*	Exit:
-;*	Modified:
-;*
-;**************************************************************************
-CPUbugIAENG2900	PROC NEAR PUBLIC
-	pushad
-
-; Clear bit 43, disables the sysenter/sysexit in CPUID3
-	mov	ecx, 3003h
-	RDMSR
-	and	edx, 0FFFFF7FFh
-	WRMSR
-
-	mov	cx, TOKEN_BTB_2900_SWAPSIF_ENABLE
-	NOSTACK	bx, GetNVRAMValueBX
-	cmp	ax, TVALUE_ENABLE
-	jne	bug2900exit
-
-
-;Disable enable_actions in DIAGCTL while setting up GLCP
-	mov	ecx, MSR_GLCP + 005fh
-	xor	edx, edx
-	xor	eax, eax
-	WRMSR
-
-;Changing DBGCLKCTL register to GeodeLink
-	mov	ecx, MSR_GLCP + 0016h
-	xor	edx, edx
-	xor	eax, eax
-	WRMSR
-
-	mov	ecx, MSR_GLCP + 0016h
-	xor	edx, edx
-	mov	eax, 02h
-	WRMSR
-
-;The code below sets up the RedCloud to stall for 4 GeodeLink clocks when CPU is snooped.
-;Because setting XSTATE to 0 overrides any other XSTATE action, the code will always
-;stall for 4 GeodeLink clocks after a snoop request goes away even if it occured a clock or two 
-;later than a different snoop; the stall signal will never 'glitch high' for 
-;only one or two CPU clocks with this code.
-
-;Send mb0 port 3 requests to upper GeodeLink diag bits [63:32]
-	mov	ecx, MSR_GLIU0 + 2005h
-	xor	edx, edx
-	mov	eax, 80338041h
-	WRMSR
-
-;set5m watches request ready from mb0 to CPU (snoop)
-	mov	ecx, MSR_GLCP + 0045h
-	mov	edx, 5ad68000h
-	xor	eax, eax
-	WRMSR
-
-;SET4M will be high when state is idle (XSTATE=11)
-	mov	ecx, MSR_GLCP + 0044h
-	xor	edx, edx
-	mov	eax, 0140h
-	WRMSR
-
-;SET5n to watch for processor stalled state
-	mov	ecx, MSR_GLCP + 004Dh
-	mov	edx, 2000h
-	xor	eax, eax
-	WRMSR
-
-;Writing action number 13: XSTATE=0 to occur when CPU is snooped unless we're stalled
-	mov	ecx, MSR_GLCP + 0075h
-	xor	edx, edx
-	mov	eax, 00400000h
-	WRMSR
-
-;Writing action number 11: inc XSTATE every GeodeLink clock unless we're idle
-	mov	ecx, MSR_GLCP + 0073h
-	xor	edx, edx
-	mov	eax, 30000h
-	WRMSR
-
-
-;Writing action number 5: STALL_CPU_PIPE when exitting idle state or not in idle state
-	mov	ecx, MSR_GLCP + 006Dh
-	xor	edx, edx
-	mov	eax, 00430000h
-	WRMSR
-
-;Writing DIAGCTL Register to enable the stall action and to let set5m watch the upper GeodeLink diag bits.
-	mov	ecx, MSR_GLCP + 005fh
-	xor	edx, edx
-	mov	eax, 80004000h
-	WRMSR
-
-
-bug2900exit:
-	popad
-	ret
-CPUbugIAENG2900	ENDP
-#endif
+	printk_debug("CPU_BUG:%s\n", __FUNCTION__);
+	/* Clear bit 43, disables the sysenter/sysexit in CPUID3 */
+	msr = rdmsr(0x3003);
+	msr.hi &= 0xFFFFF7FF;
+	wrmsr(0x3003, msr);
+
+	/* change this value to zero if you need to disable this BTB SWAPSiF. */
+	if (1) { 
+
+		/* Disable enable_actions in DIAGCTL while setting up GLCP */
+		msr.hi = 0;
+		msr.lo = 0;
+		wrmsr(MSR_GLCP + 0x005f, msr);
+
+		/* Changing DBGCLKCTL register to GeodeLink */
+		msr.hi = 0;
+		msr.lo = 0;
+		wrmsr(MSR_GLCP + 0x0016, msr);
+
+		msr.hi = 0;
+		msr.lo = 2;
+		wrmsr(MSR_GLCP + 0x0016, msr);
+
+		/* The code below sets up the CPU to stall for 4 GeodeLink 
+		 * clocks when CPU is snooped.  Because setting XSTATE to 0 
+		 * overrides any other XSTATE action, the code will always 
+		 * stall for 4 GeodeLink clocks after a snoop request goes 
+		 * away even if it occured a clock or two later than a 
+		 * different snoop; the stall signal will never 'glitch high' 
+		 * for only one or two CPU clocks with this code.
+		 */
+
+		/* Send mb0 port 3 requests to upper GeodeLink diag bits 
+		   [63:32] */
+		msr.hi = 0;
+		msr.lo = 0x80338041;
+		wrmsr(MSR_GLIU0 + 0x2005, msr);
+
+		/* set5m watches request ready from mb0 to CPU (snoop) */
+		msr.hi = 0x5ad68000;
+		msr.lo = 0;
+		wrmsr(MSR_GLCP + 0x0045, msr);
+
+		/* SET4M will be high when state is idle (XSTATE=11) */
+		msr.hi = 0;
+		msr.lo = 0x0140;
+		wrmsr(MSR_GLCP + 0x0044, msr);
+
+		/* SET5n to watch for processor stalled state */
+		msr.hi = 0x2000;
+		msr.lo = 0;
+		wrmsr(MSR_GLCP + 0x004D, msr);
+
+		/* Writing action number 13: XSTATE=0 to occur when CPU is 
+		   snooped unless we're stalled */
+		msr.hi = 0;
+		msr.lo = 0x00400000;
+		wrmsr(MSR_GLCP + 0x0075, msr);
+
+		/* Writing action number 11: inc XSTATE every GeodeLink clock 
+		   unless we're idle */
+		msr.hi = 0;
+		msr.lo = 0x30000;
+		wrmsr(MSR_GLCP + 0x0073, msr);
+
+		/* Writing action number 5: STALL_CPU_PIPE when exitting idle 
+		   state or not in idle state */
+		msr.hi = 0;
+		msr.lo = 0x00430000;
+		wrmsr(MSR_GLCP + 0x006D, msr);
+
+		/* Writing DIAGCTL Register to enable the stall action and to 
+		   let set5m watch the upper GeodeLink diag bits. */
+		msr.hi = 0;
+		msr.lo = 0x80004000;
+		wrmsr(MSR_GLCP + 0x005f, msr);
+	}
 }
 
 void bug118253(void)