X-Git-Url: http://wien.tomnetworks.com/gitweb/?a=blobdiff_plain;f=src%2Fcpu%2Famd%2Fmodel_fxx%2Fmodel_fxx_init.c;h=47eae695e85cc39bf3e335c3314587efa846f80e;hb=c02b4fc9db3c3c1e263027382697b566127f66bb;hp=8b680980192cf1f036fd54762736a65cfe1ea3f4;hpb=0f61a4fc98f135c0ed22c67ee3241bf5670a61e2;p=coreboot.git diff --git a/src/cpu/amd/model_fxx/model_fxx_init.c b/src/cpu/amd/model_fxx/model_fxx_init.c index 8b6809801..47eae695e 100644 --- a/src/cpu/amd/model_fxx/model_fxx_init.c +++ b/src/cpu/amd/model_fxx/model_fxx_init.c @@ -5,7 +5,7 @@ * 2005.02 yhlu add e0 memory hole support * Copyright 2005 AMD - * 2005.08 yhlu add microcode support + * 2005.08 yhlu add microcode support */ #include #include @@ -21,15 +21,16 @@ #include "../../../northbridge/amd/amdk8/amdk8.h" #include +#include #include #include #include -#include #include #include +#if CONFIG_WAIT_BEFORE_CPUS_INIT void cpus_ready_for_init(void) { #if CONFIG_MEM_TRAIN_SEQ == 1 @@ -38,7 +39,7 @@ void cpus_ready_for_init(void) wait_all_core0_mem_trained(sysinfox); #endif } - +#endif #if CONFIG_K8_REV_F_SUPPORT == 0 int is_e0_later_in_bsp(int nodeid) @@ -149,16 +150,16 @@ static void print_mtrr_state(struct mtrr_state *state) { int i; for(i = 0; i < MTRR_COUNT; i++) { - printk_debug("var mtrr %d: %08x%08x mask: %08x%08x\n", + printk(BIOS_DEBUG, "var mtrr %d: %08x%08x mask: %08x%08x\n", i, state->mtrrs[i].base.hi, state->mtrrs[i].base.lo, state->mtrrs[i].mask.hi, state->mtrrs[i].mask.lo); } - printk_debug("top_mem: %08x%08x\n", + printk(BIOS_DEBUG, "top_mem: %08x%08x\n", state->top_mem.hi, state->top_mem.lo); - printk_debug("top_mem2: %08x%08x\n", + printk(BIOS_DEBUG, "top_mem2: %08x%08x\n", state->top_mem2.hi, state->top_mem2.lo); - printk_debug("def_type: %08x%08x\n", + printk(BIOS_DEBUG, "def_type: %08x%08x\n", state->def_type.hi, state->def_type.lo); } #endif @@ -198,7 +199,7 @@ static void set_init_ecc_mtrrs(void) enable_cache(); } -static inline void clear_2M_ram(unsigned long basek, struct mtrr_state *mtrr_state) +static inline void clear_2M_ram(unsigned long basek, struct mtrr_state *mtrr_state) { unsigned long limitk; unsigned long size; @@ -213,7 +214,7 @@ static inline void clear_2M_ram(unsigned long basek, struct mtrr_state *mtrr_sta enable_lapic(); /* Print a status message */ - printk_debug("%c", (basek >= TOLM_KB)?'+':'-'); + printk(BIOS_DEBUG, "%c", (basek >= TOLM_KB)?'+':'-'); /* Return to the initialization state */ set_init_ecc_mtrrs(); @@ -225,19 +226,19 @@ static inline void clear_2M_ram(unsigned long basek, struct mtrr_state *mtrr_sta #if 0 /* couldn't happen, memory must on 2M boundary */ if(limitk>endk) { - limitk = enk; + limitk = enk; } #endif size = (limitk - basek) << 10; addr = map_2M_page(basek >> 11); if (addr == MAPPING_ERROR) { - printk_err("Cannot map page: %lx\n", basek >> 11); + printk(BIOS_ERR, "Cannot map page: %lx\n", basek >> 11); return; } /* clear memory 2M (limitk - basek) */ addr = (void *)(((uint32_t)addr) | ((basek & 0x7ff) << 10)); - clear_memory(addr, size); + memset(addr, 0, size); } static void init_ecc_memory(unsigned node_id) @@ -275,14 +276,14 @@ static void init_ecc_memory(unsigned node_id) } else { pci_write_config32(f3_dev, SCRUB_CONTROL, (SCRUB_NONE << 16) | (SCRUB_NONE << 8) | (SCRUB_NONE << 0)); - printk_debug("Scrubbing Disabled\n"); + printk(BIOS_DEBUG, "Scrubbing Disabled\n"); } - + /* If ecc support is not enabled don't touch memory */ dcl = pci_read_config32(f2_dev, DRAM_CONFIG_LOW); if (!(dcl & DCL_DimmEccEn)) { - printk_debug("ECC Disabled\n"); + printk(BIOS_DEBUG, "ECC Disabled\n"); return; } @@ -291,7 +292,7 @@ static void init_ecc_memory(unsigned node_id) #if CONFIG_HW_MEM_HOLE_SIZEK != 0 #if CONFIG_K8_REV_F_SUPPORT == 0 - if (!is_cpu_pre_e0()) + if (!is_cpu_pre_e0()) { #endif @@ -304,7 +305,7 @@ static void init_ecc_memory(unsigned node_id) } #endif #endif - + /* Don't start too early */ begink = startk; @@ -312,7 +313,7 @@ static void init_ecc_memory(unsigned node_id) begink = (CONFIG_RAMTOP >>10); } - printk_debug("Clearing memory %luK - %luK: ", begink, endk); + printk(BIOS_DEBUG, "Clearing memory %luK - %luK: ", begink, endk); /* Save the normal state */ save_mtrr_state(&mtrr_state); @@ -336,10 +337,10 @@ static void init_ecc_memory(unsigned node_id) clear_2M_ram(basek, &mtrr_state); } } - else + else #endif for(basek = begink; basek < endk; - basek = ((basek + ZERO_CHUNK_KB) & ~(ZERO_CHUNK_KB - 1))) + basek = ((basek + ZERO_CHUNK_KB) & ~(ZERO_CHUNK_KB - 1))) { clear_2M_ram(basek, &mtrr_state); } @@ -361,7 +362,7 @@ static void init_ecc_memory(unsigned node_id) (SCRUB_84ms << 16) | (SCRUB_84ms << 8) | (SCRUB_84ms << 0)); } - printk_debug(" done\n"); + printk(BIOS_DEBUG, " done\n"); } @@ -384,7 +385,7 @@ static inline void k8_errata(void) msr = rdmsr_amd(DC_CFG_MSR); msr.lo |= (1 << 10); wrmsr_amd(DC_CFG_MSR, msr); - + } /* I can't touch this msr on early buggy cpus */ if (!is_cpu_pre_b3()) { @@ -392,10 +393,10 @@ static inline void k8_errata(void) /* Erratum 89 ... */ msr = rdmsr(NB_CFG_MSR); msr.lo |= 1 << 3; - + if (!is_cpu_pre_c0() && is_cpu_pre_d0()) { /* D0 later don't need it */ - /* Erratum 86 Disable data masking on C0 and + /* Erratum 86 Disable data masking on C0 and * later processor revs. * FIXME this is only needed if ECC is enabled. */ @@ -403,14 +404,14 @@ static inline void k8_errata(void) } wrmsr(NB_CFG_MSR, msr); } - + /* Erratum 97 ... */ if (!is_cpu_pre_c0() && is_cpu_pre_d0()) { msr = rdmsr_amd(DC_CFG_MSR); msr.lo |= 1 << 3; wrmsr_amd(DC_CFG_MSR, msr); - } - + } + /* Erratum 94 ... */ if (is_cpu_pre_d0()) { msr = rdmsr_amd(IC_CFG_MSR); @@ -439,7 +440,7 @@ static inline void k8_errata(void) #endif #if CONFIG_K8_REV_F_SUPPORT == 0 - if (!is_cpu_pre_e0()) + if (!is_cpu_pre_e0()) #endif { /* Erratum 110 ... */ @@ -462,14 +463,11 @@ static inline void k8_errata(void) } -extern void model_fxx_update_microcode(unsigned cpu_deviceid); -int init_processor_name(void); - #if CONFIG_USBDEBUG_DIRECT static unsigned ehci_debug_addr; #endif -void model_fxx_init(device_t dev) +static void model_fxx_init(device_t dev) { unsigned long i; msr_t msr; @@ -480,12 +478,12 @@ void model_fxx_init(device_t dev) #if CONFIG_K8_REV_F_SUPPORT == 1 struct cpuinfo_x86 c; - + get_fms(&c, dev->device); #endif #if CONFIG_USBDEBUG_DIRECT - if(!ehci_debug_addr) + if(!ehci_debug_addr) ehci_debug_addr = get_ehci_debug(); set_ehci_debug(0); #endif @@ -503,7 +501,7 @@ void model_fxx_init(device_t dev) model_fxx_update_microcode(dev->device); disable_cache(); - + /* zero the machine check error status registers */ msr.lo = 0; msr.hi = 0; @@ -512,15 +510,15 @@ void model_fxx_init(device_t dev) } k8_errata(); - + /* Set SMMLOCK to avoid exploits messing with SMM */ msr = rdmsr(HWCR_MSR); msr.lo |= (1 << 0); wrmsr(HWCR_MSR, msr); - + /* Set the processor name string */ init_processor_name(); - + enable_cache(); /* Enable the local cpu apics */ @@ -531,17 +529,17 @@ void model_fxx_init(device_t dev) if(siblings>0) { msr = rdmsr_amd(CPU_ID_FEATURES_MSR); - msr.lo |= 1 << 28; + msr.lo |= 1 << 28; wrmsr_amd(CPU_ID_FEATURES_MSR, msr); msr = rdmsr_amd(LOGICAL_CPUS_NUM_MSR); - msr.lo = (siblings+1)<<16; + msr.lo = (siblings+1)<<16; wrmsr_amd(LOGICAL_CPUS_NUM_MSR, msr); msr = rdmsr_amd(CPU_ID_EXT_FEATURES_MSR); - msr.hi |= 1<<(33-32); + msr.hi |= 1<<(33-32); wrmsr_amd(CPU_ID_EXT_FEATURES_MSR, msr); - } + } #endif @@ -631,6 +629,7 @@ static struct cpu_device_id cpu_table[] = { { X86_VENDOR_AMD, 0x40fc2 }, /* DH-F2 (socket S1g1) */ { X86_VENDOR_AMD, 0x40f13 }, /* JH-F3 (socket F/1207) */ { X86_VENDOR_AMD, 0x40f33 }, /* JH-F3 (socket AM2) */ + { X86_VENDOR_AMD, 0x50fd3 }, /* JH-F3 (socket F/1207) */ { X86_VENDOR_AMD, 0xc0f13 }, /* JH-F3 (socket F/1207) */ { X86_VENDOR_AMD, 0x50ff3 }, /* DH-F3 (socket AM2) */ { X86_VENDOR_AMD, 0x60fb1 }, /* BH-G1 (socket AM2) */ @@ -639,6 +638,7 @@ static struct cpu_device_id cpu_table[] = { { X86_VENDOR_AMD, 0x60f82 }, /* BH-G2 (socket S1g1) */ { X86_VENDOR_AMD, 0x70ff1 }, /* DH-G1 (socket AM2) */ { X86_VENDOR_AMD, 0x60ff2 }, /* DH-G2 (socket AM2) */ + { X86_VENDOR_AMD, 0x70ff2 }, /* DH-G2 (socket AM2) */ { X86_VENDOR_AMD, 0x60fc2 }, /* DH-G2 (socket S1g1) */ { X86_VENDOR_AMD, 0x70fc2 }, /* DH-G2 (socket S1g1) */ #endif