X-Git-Url: http://wien.tomnetworks.com/gitweb/?a=blobdiff_plain;f=src%2Fcpu%2Famd%2Fcar%2Fpost_cache_as_ram.c;h=147a56d6183800c4642d73f74aac75b2a790edf4;hb=35ed0e7ea3d9bd6641c719cf4489bfa408e48972;hp=89366e0e3307f784c06e8b13cf6a7542f212ee33;hpb=c263b4471dd42895b409652b3f3567fcb5cdaae1;p=coreboot.git

diff --git a/src/cpu/amd/car/post_cache_as_ram.c b/src/cpu/amd/car/post_cache_as_ram.c
index 89366e0e3..147a56d61 100644
--- a/src/cpu/amd/car/post_cache_as_ram.c
+++ b/src/cpu/amd/car/post_cache_as_ram.c
@@ -7,11 +7,7 @@
 
 static inline void print_debug_pcar(const char *strval, uint32_t val)
 {
-#if CONFIG_USE_PRINTK_IN_CAR
         printk_debug("%s%08x\r\n", strval, val);
-#else
-        print_debug(strval); print_debug_hex32(val); print_debug("\r\n");
-#endif
 }
 
 static void inline __attribute__((always_inline))  memcopy(void *dest, const void *src, unsigned long bytes)
@@ -27,10 +23,10 @@ static void inline __attribute__((always_inline))  memcopy(void *dest, const voi
 
 static void vErrata343(void)
 {
+#ifdef BU_CFG2_MSR
     msr_t msr;
     unsigned int uiMask = 0xFFFFFFF7;
 
-#ifdef BU_CFG2_MSR
     msr = rdmsr(BU_CFG2_MSR);
     msr.hi &= uiMask; // set bit 35 to 0
     wrmsr(BU_CFG2_MSR, msr);
@@ -56,15 +52,15 @@ static void post_cache_as_ram(void)
 	print_debug_pcar("testx = ", testx);
 
 	/* copy data from cache as ram to 
-		ram need to set CONFIG_LB_MEM_TOPK to 2048 and use var mtrr instead.
+		ram need to set CONFIG_RAMTOP to 2M and use var mtrr instead.
 	 */
-#if CONFIG_LB_MEM_TOPK <= 1024
-        #error "You need to set CONFIG_LB_MEM_TOPK greater than 1024"
+#if CONFIG_RAMTOP <= 0x100000
+        #error "You need to set CONFIG_RAMTOP greater than 1M"
 #endif
 	
-	set_init_ram_access(); /* So we can access RAM from [1M, CONFIG_LB_MEM_TOPK) */
+	set_init_ram_access(); /* So we can access RAM from [1M, CONFIG_RAMTOP) */
 
-//	dump_mem(DCACHE_RAM_BASE+DCACHE_RAM_SIZE-0x8000, DCACHE_RAM_BASE+DCACHE_RAM_SIZE-0x7c00);
+//	dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x8000, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x7c00);
 	print_debug("Copying data from cache to RAM -- switching to use RAM as stack... ");
 
 	/* from here don't store more data in CAR */
@@ -76,14 +72,14 @@ static void post_cache_as_ram(void)
         );
 #endif
 
-        memcopy((void *)((CONFIG_LB_MEM_TOPK<<10)-DCACHE_RAM_SIZE), (void *)DCACHE_RAM_BASE, DCACHE_RAM_SIZE); //inline
-//        dump_mem((CONFIG_LB_MEM_TOPK<<10) - 0x8000, (CONFIG_LB_MEM_TOPK<<10) - 0x7c00);
+        memcopy((void *)((CONFIG_RAMTOP)-CONFIG_DCACHE_RAM_SIZE), (void *)CONFIG_DCACHE_RAM_BASE, CONFIG_DCACHE_RAM_SIZE); //inline
+//        dump_mem((CONFIG_RAMTOP) - 0x8000, (CONFIG_RAMTOP) - 0x7c00);
 
         __asm__ volatile (
-                /* set new esp */ /* before _RAMBASE */
+                /* set new esp */ /* before CONFIG_RAMBASE */
                 "subl   %0, %%ebp\n\t"
                 "subl   %0, %%esp\n\t"
-                ::"a"( (DCACHE_RAM_BASE + DCACHE_RAM_SIZE)- (CONFIG_LB_MEM_TOPK<<10) )
+                ::"a"( (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE)- (CONFIG_RAMTOP) )
         ); // We need to push %eax to the stack (CAR) before copy stack and pop it later after copy stack and change esp
 #if 0
         __asm__ volatile (
@@ -102,18 +98,18 @@ static void post_cache_as_ram(void)
 	disable_cache_as_ram_bsp();  
 
         print_debug("Clearing initial memory region: ");
-        clear_init_ram(); //except the range from [(CONFIG_LB_MEM_TOPK<<10) - DCACHE_RAM_SIZE, (CONFIG_LB_MEM_TOPK<<10))
+        clear_init_ram(); //except the range from [(CONFIG_RAMTOP) - CONFIG_DCACHE_RAM_SIZE, (CONFIG_RAMTOP))
         print_debug("Done\r\n");
 
-//	dump_mem((CONFIG_LB_MEM_TOPK<<10) - 0x8000, (CONFIG_LB_MEM_TOPK<<10) - 0x7c00);
+//	dump_mem((CONFIG_RAMTOP) - 0x8000, (CONFIG_RAMTOP) - 0x7c00);
 
-#ifndef MEM_TRAIN_SEQ
-#define MEM_TRAIN_SEQ 0
+#ifndef CONFIG_MEM_TRAIN_SEQ
+#define CONFIG_MEM_TRAIN_SEQ 0
 #endif
         set_sysinfo_in_ram(1); // So other core0 could start to train mem
 
-#if MEM_TRAIN_SEQ == 1
-//	struct sys_info *sysinfox = ((CONFIG_LB_MEM_TOPK<<10) - DCACHE_RAM_GLOBAL_VAR_SIZE);
+#if CONFIG_MEM_TRAIN_SEQ == 1
+//	struct sys_info *sysinfox = ((CONFIG_RAMTOP) - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
 
         // wait for ap memory to trained
 //        wait_all_core0_mem_trained(sysinfox); // moved to lapic_init_cpus.c