X-Git-Url: http://wien.tomnetworks.com/gitweb/?a=blobdiff_plain;f=src%2Fconsole%2FKconfig;h=f1129a1279321884dac54777cb7a8ba487a53f71;hb=1b632aff260695257b78bedc3742652916f2a724;hp=bbf4f9ddaa0af02d2611847c1297e8d1531f6a39;hpb=0364618fe86a7e3ad9b9f79105c66cbefdc64ab6;p=coreboot.git diff --git a/src/console/Kconfig b/src/console/Kconfig index bbf4f9dda..f1129a127 100644 --- a/src/console/Kconfig +++ b/src/console/Kconfig @@ -1,83 +1,223 @@ -menu "Console options" - +menu "Console" # TODO: Rename to SERIAL_CONSOLE once Kconfig transition is complete. config CONSOLE_SERIAL8250 - bool "Enable serial port console output" + bool "Serial port console output" + depends on HAVE_UART_IO_MAPPED default y help - Send coreboot debug output to a serial port console. + Send coreboot debug output to an I/O mapped serial port console. + +config CONSOLE_SERIAL8250MEM + bool "Serial port console output (memory mapped)" + depends on HAVE_UART_MEMORY_MAPPED + help + Send coreboot debug output to a memory mapped serial port console. + +choice + prompt "Serial port" + default CONSOLE_SERIAL_COM1 + depends on CONSOLE_SERIAL8250 + +config CONSOLE_SERIAL_COM1 + bool "COM1/ttyS0, I/O port 0x3f8" + help + Serial console on COM1/ttyS0 at I/O port 0x3f8. +config CONSOLE_SERIAL_COM2 + bool "COM2/ttyS1, I/O port 0x2f8" + help + Serial console on COM2/ttyS1 at I/O port 0x2f8. +config CONSOLE_SERIAL_COM3 + bool "COM3/ttyS2, I/O port 0x3e8" + help + Serial console on COM3/ttyS2 at I/O port 0x3e8. +config CONSOLE_SERIAL_COM4 + bool "COM4/ttyS3, I/O port 0x2e8" + help + Serial console on COM4/ttyS3 at I/O port 0x2e8. + +endchoice -# TODO: COM1, COM2 etc. config TTYS0_BASE - hex "I/O base for the serial port" + hex depends on CONSOLE_SERIAL8250 - default 0x3f8 + default 0x3f8 if CONSOLE_SERIAL_COM1 + default 0x2f8 if CONSOLE_SERIAL_COM2 + default 0x3e8 if CONSOLE_SERIAL_COM3 + default 0x2e8 if CONSOLE_SERIAL_COM4 + help + Map the COM port names to the respective I/O port. + +choice + prompt "Baud rate" + default CONSOLE_SERIAL_115200 + depends on CONSOLE_SERIAL8250 || CONSOLE_SERIAL8250MEM + +config CONSOLE_SERIAL_115200 + bool "115200" + help + Set serial port Baud rate to 115200. +config CONSOLE_SERIAL_57600 + bool "57600" + help + Set serial port Baud rate to 57600. +config CONSOLE_SERIAL_38400 + bool "38400" + help + Set serial port Baud rate to 38400. +config CONSOLE_SERIAL_19200 + bool "19200" + help + Set serial port Baud rate to 19200. +config CONSOLE_SERIAL_9600 + bool "9600" + help + Set serial port Baud rate to 9600. + +endchoice config TTYS0_BAUD - int "Serial port BAUD rate" - depends on CONSOLE_SERIAL8250 - default 115200 + int + default 115200 if CONSOLE_SERIAL_115200 + default 57600 if CONSOLE_SERIAL_57600 + default 38400 if CONSOLE_SERIAL_38400 + default 19200 if CONSOLE_SERIAL_19200 + default 9600 if CONSOLE_SERIAL_9600 + help + Map the Baud rates to an integer. # TODO: Allow user-friendly selection of settings other than 8n1. config TTYS0_LCS int default 3 - depends on CONSOLE_SERIAL8250 + depends on CONSOLE_SERIAL8250 || CONSOLE_SERIAL8250MEM -config SERIAL_POST - bool "Enable POST output on the serial port console" - depends on CONSOLE_SERIAL8250 - default n - help - If enabled, coreboot will additionally print POST codes (which are - usually displayed using a so-called "POST card" ISA/PCI/PCI-E - device) on the serial console. +# Use "select HAVE_USBDEBUG" on southbridges which have Debug Port code. +config HAVE_USBDEBUG + def_bool n -# TODO: FIX DEPENDENCY HERE -config USBDEBUG_DIRECT +config USBDEBUG + def_bool n + +config USBDEBUG bool "USB 2.0 EHCI debug dongle support" default n + depends on HAVE_USBDEBUG help This option allows you to use a so-called USB EHCI Debug device + (such as the Ajays NET20DC, AMIDebug RX, or a system using the + Linux "EHCI Debug Device gadget" driver found in recent kernel) to retrieve the coreboot debug messages (instead, or in addition to, a serial port). This feature is NOT supported on all chipsets in coreboot! It also requires a USB2 controller which supports the EHCI - Debug Port capability. Controllers which are known to work: - - * 10b9:5239 ALi Corporation USB 2.0 (USB PCI card) - * 8086:24cd Intel ICH4/ICH4-M - * 8086:24dd Intel ICH5 - * 8086:265c Intel ICH6 - * 8086:268c Intel 631xESB/632xESB/3100 - * 8086:27cc Intel ICH7 - * 8086:2836 Intel ICH8 - * 8086:283a Intel ICH8 - * 8086:293a Intel ICH9 - * 10de:0088 NVIDIA MCP2A - * 10de:005b NVIDIA CK804 - * 10de:026e NVIDIA MCP51 - * 10de:036d NVIDIA MCP55 - * 10de:03f2 NVIDIA MCP61 - * 1002:4386 ATI/AMD SB600 - * 1106:3104 VIA VX800 - - See http://www.coreboot.org/EHCI_Debug_Port for an up-to-date list. - -config CONSOLE_VGA - bool "Use VGA console once initialized" - default n + Debug Port capability. + + See http://www.coreboot.org/EHCI_Debug_Port for an up-to-date list + of supported controllers. + + If unsure, say N. + +# Note: This option doesn't make sense on Intel ICH / AMD SB600 southbridges +# as those hardcode the physical USB port to be used as Debug Port to 1. +# It cannot be changed by coreboot. +config USBDEBUG_DEFAULT_PORT + int "Default USB port to use as Debug Port" + default 1 + depends on USBDEBUG && !SOUTHBRIDGE_INTEL_I82801GX && !SOUTHBRIDGE_AMD_SB600 + help + This option selects which physical USB port coreboot will try to + use as EHCI Debug Port first (valid values are: 1-15). + + If coreboot doesn't detect an EHCI Debug Port dongle on this port, + it will try all the other ports one after the other. This will take + a few seconds of time though, and thus slow down the booting process. + + Hence, if you select the correct port here, you can speed up + your boot time. Which USB port number (1-15) refers to which + actual port on your mainboard (potentially also USB pin headers + on your mainboard) is highly board-specific, and you'll likely + have to find out by trial-and-error. # TODO: Deps? # TODO: Improve description. -config CONSOLE_VGA_ONBOARD_AT_FIRST +config ONBOARD_VGA_IS_PRIMARY bool "Use onboard VGA as primary video device" default n help If not selected, the last adapter found will be used. +config CONSOLE_NE2K + bool "Network console over NE2000 compatible Ethernet adapter" + default n + help + Send coreboot debug output to a Ethernet console, it works + same way as Linux netconsole, packets are received to UDP + port 6666 on IP/MAC specified with options bellow. + Use following netcat command: nc -u -l -p 6666 + +config CONSOLE_NE2K_DST_MAC + depends on CONSOLE_NE2K + string "Destination MAC address of remote system" + default "00:13:d4:76:a2:ac" + help + Type in either MAC address of logging system or MAC address + of the router. + +config CONSOLE_NE2K_DST_IP + depends on CONSOLE_NE2K + string "Destination IP of logging system" + default "10.0.1.27" + help + This is IP adress of the system running for example + netcat command to dump the packets. + +config CONSOLE_NE2K_SRC_IP + depends on CONSOLE_NE2K + string "IP address of coreboot system" + default "10.0.1.253" + help + This is the IP of the coreboot system + +config CONSOLE_NE2K_IO_PORT + depends on CONSOLE_NE2K + hex "NE2000 adapter fixed IO port address" + default 0xe00 + help + This is the IO port address for the IO port + on the card, please select some non-conflicting region, + 32 bytes of IO spaces will be used (and align on 32 bytes + boundary, qemu needs broader align) + +config CONSOLE_CBMEM + depends on EARLY_CBMEM_INIT + bool "Send console output to a CBMEM buffer" + default n + help + Enable this to save the console output in a CBMEM buffer. This would + allow to see coreboot console output from Linux space. + +config CONSOLE_CBMEM_BUFFER_SIZE + depends on CONSOLE_CBMEM + hex "Room allocated for console output in CBMEM" + default 0x10000 + help + Space allocated for console output storage in CBMEM. The default + value (64K or 0x10000 bytes) is large enough to accommodate + even the BIOS_SPEW level. + +config CONSOLE_CAR_BUFFER_SIZE + depends on CONSOLE_CBMEM + hex "Room allocated for console output in Cache as RAM" + default 0xc00 + help + Console is used before RAM is initialized. This is the room reserved + in the DCACHE based RAM to keep console output before it can be + saved in a CBMEM buffer. 3K bytes should be enough even for the + BIOS_SPEW level. + + choice prompt "Maximum console log level" default MAXIMUM_CONSOLE_LOGLEVEL_8 @@ -212,5 +352,26 @@ config DEFAULT_CONSOLE_LOGLEVEL help Map the log level config names to an integer. +config CONSOLE_LOGBUF + bool + default n + +config NO_POST + bool "Don't show any POST codes" + default n + +config POST_PORT + hex + default 0x80 + +config CONSOLE_POST + bool "Show POST codes on the debug console" + depends on !NO_POST + default n + help + If enabled, coreboot will additionally print POST codes (which are + usually displayed using a so-called "POST card" ISA/PCI/PCI-E + device) on the debug console. + endmenu