X-Git-Url: http://wien.tomnetworks.com/gitweb/?a=blobdiff_plain;f=src%2Fclock.c;h=d88515c45c482153144365c90b099c465b5076e8;hb=b29200c51beb1e75e7f844a4093da05b8394ad5e;hp=7735c70a3e994eaeb26405652aecc37c1f64200e;hpb=89eb6241e51bc825cfbc1292802a960dcb48d778;p=seabios.git diff --git a/src/clock.c b/src/clock.c index 7735c70..d88515c 100644 --- a/src/clock.c +++ b/src/clock.c @@ -1,6 +1,6 @@ // 16bit code to handle system clocks. // -// Copyright (C) 2008 Kevin O'Connor +// Copyright (C) 2008-2010 Kevin O'Connor // Copyright (C) 2002 MandrakeSoft S.A. // // This file may be distributed under the terms of the GNU LGPLv3 license. @@ -12,7 +12,7 @@ #include "pic.h" // eoi_pic1 #include "bregs.h" // struct bregs #include "biosvar.h" // GET_GLOBAL -#include "usb-hid.h" // usb_check_key +#include "usb-hid.h" // usb_check_event // RTC register flags #define RTC_A_UIP 0x80 @@ -48,23 +48,40 @@ #define PM_MODE5 (5<<1) #define PM_CNT_BINARY (0<<0) #define PM_CNT_BCD (1<<0) +#define PM_READ_COUNTER0 (1<<1) +#define PM_READ_COUNTER1 (1<<2) +#define PM_READ_COUNTER2 (1<<3) +#define PM_READ_STATUSVALUE (0<<4) +#define PM_READ_VALUE (1<<4) +#define PM_READ_STATUS (2<<4) /**************************************************************** * TSC timer ****************************************************************/ -#define PIT_TICK_RATE 1193180 // Underlying HZ of PIT -#define PIT_TICK_INTERVAL 65536 // Default interval for 18.2Hz timer -#define TICKS_PER_DAY (u32)((u64)60*60*24*PIT_TICK_RATE / PIT_TICK_INTERVAL) #define CALIBRATE_COUNT 0x800 // Approx 1.7ms u32 cpu_khz VAR16VISIBLE; +u8 no_tsc VAR16VISIBLE; static void -calibrate_tsc() +calibrate_tsc(void) { + u32 eax, ebx, ecx, edx, cpuid_features = 0; + cpuid(0, &eax, &ebx, &ecx, &edx); + if (eax > 0) + cpuid(1, &eax, &ebx, &ecx, &cpuid_features); + + if (!(cpuid_features & CPUID_TSC)) { + SET_GLOBAL(no_tsc, 1); + SET_GLOBAL(cpu_khz, PIT_TICK_RATE / 1000); + dprintf(3, "386/486 class CPU. Using TSC emulation\n"); + return; + } + // Setup "timer2" +#if 0 u8 orig = inb(PORT_PS2_CTRLB); outb((orig & ~PPCB_SPKR) | PPCB_T2GATE, PORT_PS2_CTRLB); /* binary, mode 0, LSB/MSB, Ch 2 */ @@ -88,36 +105,83 @@ calibrate_tsc() , (u32)start, (u32)end, (u32)diff); u32 hz = diff * PIT_TICK_RATE / CALIBRATE_COUNT; SET_GLOBAL(cpu_khz, hz / 1000); +#else + u32 hz = 800 * 1000000; + SET_GLOBAL(cpu_khz, hz / 1000); +#endif dprintf(1, "CPU Mhz=%u\n", hz / 1000000); } +static u64 +emulate_tsc(void) +{ + int cnt, d; + u16 ebda_seg = get_ebda_seg(); + u64 ret; + /* read timer 0 current count */ + ret = GET_EBDA2(ebda_seg, tsc_8254); + /* readback mode has slightly shifted registers, works on all 8254, readback PIT0 latch */ + outb(PM_SEL_READBACK | PM_READ_VALUE | PM_READ_COUNTER0, PORT_PIT_MODE); + cnt = (inb(PORT_PIT_COUNTER0) | (inb(PORT_PIT_COUNTER0) << 8)); + d = GET_EBDA2(ebda_seg, last_tsc_8254) - cnt; + /* Determine the ticks count from last invocation of this function */ + ret += (d > 0) ? d : (PIT_TICK_INTERVAL + d); + SET_EBDA2(ebda_seg, last_tsc_8254, cnt); + SET_EBDA2(ebda_seg, tsc_8254, ret); + return ret; +} + +static u64 +get_tsc(void) +{ + if (unlikely(GET_GLOBAL(no_tsc))) + return emulate_tsc(); + return rdtscll(); +} + +int +check_tsc(u64 end) +{ + return (s64)(get_tsc() - end) > 0; +} + static void tscdelay(u64 diff) { - u64 start = rdtscll(); + u64 start = get_tsc(); u64 end = start + diff; - while (!check_time(end)) + while (!check_tsc(end)) cpu_relax(); } -void -ndelay(u32 count) +static void +tscsleep(u64 diff) { - u32 khz = GET_GLOBAL(cpu_khz); - tscdelay(count * khz / 1000000); + u64 start = get_tsc(); + u64 end = start + diff; + while (!check_tsc(end)) + yield(); } -void -udelay(u32 count) -{ - u32 khz = GET_GLOBAL(cpu_khz); - tscdelay(count * khz / 1000); + +void ndelay(u32 count) { + tscdelay(count * GET_GLOBAL(cpu_khz) / 1000000); } -void -mdelay(u32 count) -{ - u32 khz = GET_GLOBAL(cpu_khz); - tscdelay(count * khz); +void udelay(u32 count) { + tscdelay(count * GET_GLOBAL(cpu_khz) / 1000); +} +void mdelay(u32 count) { + tscdelay(count * GET_GLOBAL(cpu_khz)); +} + +void nsleep(u32 count) { + tscsleep(count * GET_GLOBAL(cpu_khz) / 1000000); +} +void usleep(u32 count) { + tscsleep(count * GET_GLOBAL(cpu_khz) / 1000); +} +void msleep(u32 count) { + tscsleep(count * GET_GLOBAL(cpu_khz)); } // Return the TSC value that is 'msecs' time in the future. @@ -125,13 +189,13 @@ u64 calc_future_tsc(u32 msecs) { u32 khz = GET_GLOBAL(cpu_khz); - return rdtscll() + ((u64)khz * msecs); + return get_tsc() + ((u64)khz * msecs); } u64 calc_future_tsc_usec(u32 usecs) { u32 khz = GET_GLOBAL(cpu_khz); - return rdtscll() + ((u64)(khz/1000) * usecs); + return get_tsc() + ((u64)(khz/1000) * usecs); } @@ -140,7 +204,7 @@ calc_future_tsc_usec(u32 usecs) ****************************************************************/ static int -rtc_updating() +rtc_updating(void) { // This function checks to see if the update-in-progress bit // is set in CMOS Status Register A. If not, it returns 0. @@ -148,22 +212,23 @@ rtc_updating() // to 0, and will return 0 if such a transition occurs. A -1 // is returned only after timing out. The maximum period // that this bit should be set is constrained to (1984+244) - // useconds, so we wait for 3 msec max. + // useconds, but we wait for longer just to be sure. if ((inb_cmos(CMOS_STATUS_A) & RTC_A_UIP) == 0) return 0; - u64 end = calc_future_tsc(3); - do { + u64 end = calc_future_tsc(15); + for (;;) { if ((inb_cmos(CMOS_STATUS_A) & RTC_A_UIP) == 0) return 0; - } while (!check_time(end)); - - // update-in-progress never transitioned to 0 - return -1; + if (check_tsc(end)) + // update-in-progress never transitioned to 0 + return -1; + yield(); + } } static void -pit_setup() +pit_setup(void) { // timer0: binary count, 16bit count, mode 2 outb(PM_SEL_TIMER0|PM_ACCESS_WORD|PM_MODE2|PM_CNT_BINARY, PORT_PIT_MODE); @@ -173,7 +238,7 @@ pit_setup() } static void -init_rtc() +init_rtc(void) { outb_cmos(0x26, CMOS_STATUS_A); // 32,768Khz src, 976.5625us updates u8 regB = inb_cmos(CMOS_STATUS_B); @@ -189,24 +254,37 @@ bcd2bin(u8 val) } void -timer_setup() +timer_setup(void) { dprintf(3, "init timer\n"); +#if 1 calibrate_tsc(); +#endif + dprintf(3, "init timer: 01\n"); pit_setup(); + dprintf(3, "init timer: 02\n"); init_rtc(); + dprintf(3, "init timer: 03\n"); rtc_updating(); + dprintf(3, "init timer: 04\n"); u32 seconds = bcd2bin(inb_cmos(CMOS_RTC_SECONDS)); + dprintf(3, "init timer: 05\n"); u32 minutes = bcd2bin(inb_cmos(CMOS_RTC_MINUTES)); + dprintf(3, "init timer: 06\n"); u32 hours = bcd2bin(inb_cmos(CMOS_RTC_HOURS)); + dprintf(3, "init timer: 07\n"); u32 ticks = (hours * 60 + minutes) * 60 + seconds; + dprintf(3, "init timer: 08\n"); ticks = ((u64)ticks * PIT_TICK_RATE) / PIT_TICK_INTERVAL; + dprintf(3, "init timer: 09\n"); SET_BDA(timer_counter, ticks); - SET_BDA(timer_rollover, 0); + dprintf(3, "init timer: 10\n"); - enable_hwirq(0, entry_08); - enable_hwirq(8, entry_70); + enable_hwirq(0, FUNC16(entry_08)); + dprintf(3, "init timer: 11\n"); + enable_hwirq(8, FUNC16(entry_70)); + dprintf(3, "init timer: 12\n"); } @@ -214,10 +292,40 @@ timer_setup() * Standard clock functions ****************************************************************/ +#define TICKS_PER_DAY (u32)((u64)60*60*24*PIT_TICK_RATE / PIT_TICK_INTERVAL) + +// Calculate the timer value at 'count' number of full timer ticks in +// the future. +u32 +calc_future_timer_ticks(u32 count) +{ + return (GET_BDA(timer_counter) + count + 1) % TICKS_PER_DAY; +} + +// Return the timer value that is 'msecs' time in the future. +u32 +calc_future_timer(u32 msecs) +{ + if (!msecs) + return GET_BDA(timer_counter); + u32 kticks = DIV_ROUND_UP((u64)msecs * PIT_TICK_RATE, PIT_TICK_INTERVAL); + u32 ticks = DIV_ROUND_UP(kticks, 1000); + return calc_future_timer_ticks(ticks); +} + +// Check if the given timer value has passed. +int +check_timer(u32 end) +{ + return (((GET_BDA(timer_counter) + TICKS_PER_DAY - end) % TICKS_PER_DAY) + < (TICKS_PER_DAY/2)); +} + // get current clock count static void handle_1a00(struct bregs *regs) { + yield(); u32 ticks = GET_BDA(timer_counter); regs->cx = ticks >> 16; regs->dx = ticks; @@ -243,7 +351,7 @@ static void handle_1a02(struct bregs *regs) { if (rtc_updating()) { - set_fail(regs); + set_invalid(regs); return; } @@ -292,7 +400,7 @@ handle_1a04(struct bregs *regs) { regs->ah = 0; if (rtc_updating()) { - set_fail(regs); + set_invalid(regs); return; } regs->cl = inb_cmos(CMOS_RTC_YEAR); @@ -326,7 +434,7 @@ handle_1a05(struct bregs *regs) // My assumption: RegB = (RegB & 01111111b) if (rtc_updating()) { init_rtc(); - set_fail(regs); + set_invalid(regs); return; } outb_cmos(regs->cl, CMOS_RTC_YEAR); @@ -360,7 +468,7 @@ handle_1a06(struct bregs *regs) regs->ax = 0; if (val8 & RTC_B_AIE) { // Alarm interrupt enabled already - set_fail(regs); + set_invalid(regs); return; } if (rtc_updating()) { @@ -401,7 +509,7 @@ handle_1a07(struct bregs *regs) static void handle_1aXX(struct bregs *regs) { - set_fail(regs); + set_unimplemented(regs); } // INT 1Ah Time-of-day Service Entry Point @@ -425,7 +533,7 @@ handle_1a(struct bregs *regs) // INT 08h System Timer ISR Entry Point void VISIBLE16 -handle_08() +handle_08(void) { debug_isr(DEBUG_ISR_08); @@ -442,7 +550,7 @@ handle_08() SET_BDA(timer_counter, counter); - usb_check_key(); + usb_check_event(); // chain to user timer tick INT #0x1c u32 eax=0, flags; @@ -456,6 +564,32 @@ handle_08() * Periodic timer ****************************************************************/ +void +useRTC(void) +{ + u16 ebda_seg = get_ebda_seg(); + int count = GET_EBDA2(ebda_seg, RTCusers); + SET_EBDA2(ebda_seg, RTCusers, count+1); + if (count) + return; + // Turn on the Periodic Interrupt timer + u8 bRegister = inb_cmos(CMOS_STATUS_B); + outb_cmos(bRegister | RTC_B_PIE, CMOS_STATUS_B); +} + +void +releaseRTC(void) +{ + u16 ebda_seg = get_ebda_seg(); + int count = GET_EBDA2(ebda_seg, RTCusers); + SET_EBDA2(ebda_seg, RTCusers, count-1); + if (count != 1) + return; + // Clear the Periodic Interrupt. + u8 bRegister = inb_cmos(CMOS_STATUS_B); + outb_cmos(bRegister & ~RTC_B_PIE, CMOS_STATUS_B); +} + static int set_usertimer(u32 usecs, u16 seg, u16 offset) { @@ -466,22 +600,18 @@ set_usertimer(u32 usecs, u16 seg, u16 offset) SET_BDA(rtc_wait_flag, RWS_WAIT_PENDING); // Set status byte. SET_BDA(user_wait_complete_flag, SEGOFF(seg, offset)); SET_BDA(user_wait_timeout, usecs); - - // Turn on the Periodic Interrupt timer - u8 bRegister = inb_cmos(CMOS_STATUS_B); - outb_cmos(bRegister | RTC_B_PIE, CMOS_STATUS_B); - + useRTC(); return 0; } static void -clear_usertimer() +clear_usertimer(void) { + if (!(GET_BDA(rtc_wait_flag) & RWS_WAIT_PENDING)) + return; // Turn off status byte. SET_BDA(rtc_wait_flag, 0); - // Clear the Periodic Interrupt. - u8 bRegister = inb_cmos(CMOS_STATUS_B); - outb_cmos(bRegister & ~RTC_B_PIE, CMOS_STATUS_B); + releaseRTC(); } #define RET_ECLOCKINUSE 0x83 @@ -495,7 +625,7 @@ handle_1586(struct bregs *regs) u32 count = (regs->cx << 16) | regs->dx; int ret = set_usertimer(count, GET_SEG(SS), (u32)&statusflag); if (ret) { - set_code_fail(regs, RET_ECLOCKINUSE); + set_code_invalid(regs, RET_ECLOCKINUSE); return; } while (!statusflag) @@ -510,7 +640,7 @@ handle_158300(struct bregs *regs) int ret = set_usertimer((regs->cx << 16) | regs->dx, regs->es, regs->bx); if (ret) // Interval already set. - set_code_fail(regs, RET_EUNSUPPORTED); + set_code_invalid(regs, RET_EUNSUPPORTED); else set_success(regs); } @@ -526,7 +656,7 @@ handle_158301(struct bregs *regs) static void handle_1583XX(struct bregs *regs) { - set_code_fail(regs, RET_EUNSUPPORTED); + set_code_unimplemented(regs, RET_EUNSUPPORTED); regs->al--; } @@ -544,7 +674,7 @@ handle_1583(struct bregs *regs) // int70h: IRQ8 - CMOS RTC void VISIBLE16 -handle_70() +handle_70(void) { debug_isr(DEBUG_ISR_70); @@ -564,6 +694,8 @@ handle_70() // Handle Periodic Interrupt. + check_preempt(); + if (!GET_BDA(rtc_wait_flag)) goto done;