X-Git-Url: http://wien.tomnetworks.com/gitweb/?a=blobdiff_plain;f=src%2Fcalc_s3e.vhd;h=3c67b22a9ddad56fc4ce1c6899c9da2e2156c2f0;hb=51361c5dc1ab06332a04260f5192adcb398238e6;hp=040034ad3ec94bd49496f72f503241d0cd7d12b4;hpb=34190ffd9a15162c9f87dfd802ec33f472a43783;p=hwmod.git

diff --git a/src/calc_s3e.vhd b/src/calc_s3e.vhd
index 040034a..3c67b22 100644
--- a/src/calc_s3e.vhd
+++ b/src/calc_s3e.vhd
@@ -12,8 +12,8 @@ entity calc is
 	port (
 		CLK_50MHZ : in std_logic;
 		sys_res : in std_logic;
-		-- btnA
-		-- TODO: pins
+		-- btnA (here: "btn west")
+		btn_a : in std_logic;
 		-- rs232
 		rxd : in std_logic;
 		txd : out std_logic;
@@ -30,6 +30,8 @@ entity calc is
 end entity calc;
 
 architecture top of calc is
+	constant CLK_FREQ : integer := 50000000;
+	constant BAUDRATE : integer := 115200;
 	-- reset
 	signal sys_res_n : std_logic;
 	-- ps/2
@@ -57,6 +59,12 @@ architecture top of calc is
 	signal p_wdone : std_logic;
 	signal p_write : hbyte;
 	signal p_finished : std_logic;
+	--history/pc_com
+	signal pc_get : std_logic;
+	signal pc_spalte : hspalte;
+	signal pc_zeile : hzeile;
+	signal pc_char : hbyte;
+	signal pc_done : std_logic;
 	-- parser/scanner
 	signal do_it, finished : std_logic;
 	-- rs232
@@ -142,7 +150,13 @@ begin
 		p_wtake => p_wtake,
 		p_wdone => p_wdone,
 		p_write => p_write,
-		p_finished => p_finished
+		p_finished => p_finished,
+		-- pc communication
+		pc_get =>  pc_get,
+		pc_spalte => pc_spalte,
+		pc_zeile => pc_zeile,
+		pc_char => pc_char,
+		pc_done => pc_done
 	);
 
 	-- parser
@@ -184,7 +198,7 @@ begin
 	-- ps/2
 	ps2_inst : entity work.ps2_keyboard_controller(beh)
 	generic map (
-		CLK_FREQ => 50000000,
+		CLK_FREQ => CLK_FREQ,
 		SYNC_STAGES => 2
 	)
 	port map (
@@ -213,8 +227,8 @@ begin
 	-- rs232-rx
 	rs232rx_inst : entity work.uart_rx(beh)
 	generic map (
-		CLK_FREQ => 50000000,
-		BAUDRATE => 115200
+		CLK_FREQ => CLK_FREQ,
+		BAUDRATE => BAUDRATE
 	)
 	port map (
 		sys_clk => CLK_50MHZ,
@@ -227,8 +241,8 @@ begin
 	-- rs232-tx
 	rs232tx_inst : entity work.uart_tx(beh)
 	generic map (
-		CLK_FREQ => 50000000,
-		BAUDRATE => 115200
+		CLK_FREQ => CLK_FREQ,
+		BAUDRATE => BAUDRATE
 	)
 	port map (
 		sys_clk => CLK_50MHZ,
@@ -238,4 +252,26 @@ begin
 		tx_new => tx_new,
 		tx_done => tx_done
 	);
+
+	-- pc-com
+	pc_com_inst : entity work.pc_communication(beh)
+	port map (
+		sys_clk => CLK_50MHZ,
+		sys_res_n => sys_res_n,
+		--button
+		btn_a => not btn_a,
+		--uart_tx
+		tx_data => tx_data,
+		tx_new => tx_new,
+		tx_done => tx_done,
+		--uart_rx
+		rx_data => rx_data,
+		rx_new => rx_new,
+		-- History
+		pc_zeile => pc_zeile,
+		pc_spalte => pc_spalte,
+		pc_get => pc_get,
+		pc_done => pc_done,
+		pc_char => pc_char
+	);
 end architecture top;