X-Git-Url: http://wien.tomnetworks.com/gitweb/?a=blobdiff_plain;f=src%2Fcalc.vhd;h=20d2027e62013e409327ac531a1f4792612e3207;hb=51361c5dc1ab06332a04260f5192adcb398238e6;hp=7347002dcd823619e8d00e7ef18358d3f9a41645;hpb=9bbe2b05fdf9bce3b58a2cabd54f69da1d09e4f8;p=hwmod.git diff --git a/src/calc.vhd b/src/calc.vhd index 7347002..20d2027 100644 --- a/src/calc.vhd +++ b/src/calc.vhd @@ -1,63 +1,307 @@ --- TODO: dient im moment nur als "fake top entity" library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use work.gen_pkg.all; +use work.textmode_vga_component_pkg.all; +use work.textmode_vga_pkg.all; +use work.textmode_vga_platform_dependent_pkg.all; +use work.ps2_keyboard_controller_pkg.all; +use work.debounce_pkg.all; +use work.sync_pkg.all; entity calc is - port - ( + port ( sys_clk : in std_logic; - sys_res_n : in std_logic + sys_res_n : in std_logic; + -- btnA + btn_a : in std_logic; + -- rs232 + rxd : in std_logic; + txd : out std_logic; + -- vga + vsync_n : out std_logic; + hsync_n : out std_logic; + r : out std_logic_vector(RED_BITS - 1 downto 0); + g : out std_logic_vector(GREEN_BITS - 1 downto 0); + b : out std_logic_vector(BLUE_BITS - 1 downto 0); + -- ps/2 + ps2_clk : inout std_logic; + ps2_data : inout std_logic ); end entity calc; architecture top of calc is - component alu is - port - ( - sys_clk : in std_logic; - sys_res_n : in std_logic; - opcode : in alu_ops; - op1 : in csigned; - op2 : in csigned; - op3 : out csigned; - do_calc : in std_logic; - calc_done : out std_logic - ); - end component alu; - - signal do_calc, calc_done : std_logic; - signal opcode : alu_ops; - signal op1, op2, op3 : csigned; + constant CLK_FREQ : integer := 33000000; + constant BAUDRATE : integer := 115200; + -- ps/2 + signal new_data : std_logic; + signal data : std_logic_vector(7 downto 0); + -- vga + signal vga_clk, free : std_logic; + -- vga/display + signal command : std_logic_vector(COMMAND_SIZE - 1 downto 0); + signal command_data : std_logic_vector(3 * COLOR_SIZE + CHAR_SIZE -1 downto 0); + -- history/display + signal d_new_eingabe, d_new_result, d_new_bs : std_logic; + signal d_zeile : hzeile; + signal d_spalte : hspalte; + signal d_get, d_done : std_logic; + signal d_char : hbyte; + -- history/scanner + signal s_char : hbyte; + signal s_take, s_done, s_backspace : std_logic; + -- history/parser + signal p_rget : std_logic; + signal p_rdone : std_logic; + signal p_read : hbyte; + signal p_wtake : std_logic; + signal p_wdone : std_logic; + signal p_write : hbyte; + signal p_finished : std_logic; + --history/pc_com + signal pc_get : std_logic; + signal pc_spalte : hspalte; + signal pc_zeile : hzeile; + signal pc_char : hbyte; + signal pc_done : std_logic; + -- parser/scanner + signal do_it, finished : std_logic; + -- debouncing + signal sys_res_n_sync : std_logic; + signal btn_a_sync : std_logic; + -- rs232 + signal rx_new, rxd_sync : std_logic; + signal rx_data : std_logic_vector (7 downto 0); + signal tx_new, tx_done : std_logic; + signal tx_data : std_logic_vector (7 downto 0); begin - aluc : alu - port map - ( + -- vga/ipcore + textmode_vga_inst : textmode_vga + generic map ( + VGA_CLK_FREQ => 25000000, + BLINK_INTERVAL_MS => 500, + SYNC_STAGES => 2 + ) + port map ( + sys_clk => sys_clk, + sys_res_n => sys_res_n_sync, + command => command, + command_data => command_data, + free => free, + vga_clk => vga_clk, + vga_res_n => sys_res_n_sync, + vsync_n => vsync_n, + hsync_n => hsync_n, + r => r, + g => g, + b => b + ); + + -- pll fuer vga + vpll_inst : vpll + port map ( + inclk0 => sys_clk, + c0 => vga_clk + ); + + -- display + display_inst : display + port map ( + sys_clk => sys_clk, + sys_res_n => sys_res_n_sync, + -- history + d_new_eingabe => d_new_eingabe, + d_new_result => d_new_result, + d_new_bs => d_new_bs, + d_zeile => d_zeile, + d_spalte => d_spalte, + d_get => d_get, + d_done => d_done, + d_char => d_char, + -- vga + command => command, + command_data => command_data, + free => free + ); + + -- history + history_inst : history + port map ( + sys_clk => sys_clk, + sys_res_n => sys_res_n_sync, + -- scanner + s_char => s_char, + s_take => s_take, + s_done => s_done, + s_backspace => s_backspace, + -- display + d_new_eingabe => d_new_eingabe, + d_new_result => d_new_result, + d_new_bs => d_new_bs, + d_zeile => d_zeile, + d_spalte => d_spalte, + d_get => d_get, + d_done => d_done, + d_char => d_char, + -- parser + p_rget => p_rget, + p_rdone => p_rdone, + p_read => p_read, + p_wtake => p_wtake, + p_wdone => p_wdone, + p_write => p_write, + p_finished => p_finished, + -- pc communication + pc_get => pc_get, + pc_spalte => pc_spalte, + pc_zeile => pc_zeile, + pc_char => pc_char, + pc_done => pc_done + ); + + -- parser + parser_inst : parser + port map ( + sys_clk => sys_clk, + sys_res_n => sys_res_n_sync, + -- history + p_rget => p_rget, + p_rdone => p_rdone, + p_read => p_read, + p_wtake => p_wtake, + p_wdone => p_wdone, + p_write => p_write, + p_finished => p_finished, + -- scanner + do_it => do_it, + finished => finished + ); + + -- scanner + scanner_inst : scanner + port map ( + sys_clk => sys_clk, + sys_res_n => sys_res_n_sync, + -- ps/2 + new_data => new_data, + data => data, + -- history + s_char => s_char, + s_take => s_take, + s_done => s_done, + s_backspace => s_backspace, + -- parser + do_it => do_it, + finished => finished + ); + + -- ps/2 + ps2_inst : ps2_keyboard_controller + generic map ( + CLK_FREQ => CLK_FREQ, + SYNC_STAGES => 2 + ) + port map ( + sys_clk => sys_clk, + sys_res_n => sys_res_n_sync, + -- scanner + new_data => new_data, + data => data, + ps2_clk => ps2_clk, + ps2_data => ps2_data + ); + + -- debouncer fuer sys_res_n + sys_res_n_debounce_inst : debounce + generic map ( + CLK_FREQ => CLK_FREQ, + TIMEOUT => 1 ms, + RESET_VALUE => '1', + SYNC_STAGES => 2 + ) + port map ( + sys_clk => sys_clk, + sys_res_n => '1', + data_in => sys_res_n, + data_out => sys_res_n_sync + ); + + -- synchronizer fuer rxd + sync_rxd_inst : sync + generic map ( + SYNC_STAGES => 2, + RESET_VALUE => '1' + ) + port map ( + sys_clk => sys_clk, + sys_res_n => sys_res_n_sync, + data_in => rxd, + data_out => rxd_sync + ); + + -- debouncer fuer btn_a + btn_a_debounce_inst : debounce + generic map ( + CLK_FREQ => CLK_FREQ, + TIMEOUT => 1 ms, + RESET_VALUE => '1', + SYNC_STAGES => 2 + ) + port map ( + sys_clk => sys_clk, + sys_res_n => sys_res_n_sync, + data_in => btn_a, + data_out => btn_a_sync + ); + + -- rs232-rx + rs232rx_inst : uart_rx + generic map ( + CLK_FREQ => CLK_FREQ, + BAUDRATE => BAUDRATE + ) + port map ( + sys_clk => sys_clk, + sys_res_n => sys_res_n_sync, + rxd => rxd_sync, + rx_data => rx_data, + rx_new => rx_new + ); + + -- rs232-tx + rs232tx_inst : uart_tx + generic map ( + CLK_FREQ => CLK_FREQ, + BAUDRATE => BAUDRATE + ) + port map ( sys_clk => sys_clk, sys_res_n => sys_res_n, - do_calc => do_calc, - calc_done => calc_done, - op1 => op1, - op2 => op2, - op3 => op3, - opcode => opcode - ); - - process (sys_clk, sys_res_n) - begin - if sys_res_n = '0' then - op1 <= (others => '0'); - opcode <= NOP; - op2 <= (others => '0'); - do_calc <= '0'; - elsif rising_edge(sys_clk) then - op1 <= op3; - opcode <= DIV; - op2 <= to_signed(2,CBITS); - - do_calc <= calc_done; - end if; - end process; -end architecture top; + txd => txd, + tx_data => tx_data, + tx_new => tx_new, + tx_done => tx_done + ); + pc_com_inst : pc_communication + port map ( + sys_clk => sys_clk, + sys_res_n => sys_res_n, + --button + btn_a => btn_a_sync, + --uart_tx + tx_data => tx_data, + tx_new => tx_new, + tx_done => tx_done, + --uart_rx + rx_data => rx_data, + rx_new => rx_new, + -- History + pc_zeile => pc_zeile, + pc_spalte => pc_spalte, + pc_get => pc_get, + pc_done => pc_done, + pc_char => pc_char + ); + +end architecture top;