X-Git-Url: http://wien.tomnetworks.com/gitweb/?a=blobdiff_plain;f=src%2Fboot%2Fhardwaremain.c;h=489caa39a594ae5e5293bad06b7704a65e8b197a;hb=bf729baa2c7b2fbfa03e271c4f3f5707989e43b5;hp=686b09576fbec249cc96383de33b7ea454514037;hpb=de3206a7bebce99f11e753164cc4d46357bba96a;p=coreboot.git

diff --git a/src/boot/hardwaremain.c b/src/boot/hardwaremain.c
index 686b09576..489caa39a 100644
--- a/src/boot/hardwaremain.c
+++ b/src/boot/hardwaremain.c
@@ -41,14 +41,15 @@ it with the version available from LANL.
 #if CONFIG_WRITE_HIGH_TABLES
 #include <cbmem.h>
 #endif
+#include <timestamp.h>
 
 /**
  * @brief Main function of the RAM part of coreboot.
  *
- * Coreboot is divided into Pre-RAM part and RAM part. 
- * 
+ * Coreboot is divided into Pre-RAM part and RAM part.
+ *
  * Device Enumeration:
- *	In the dev_enumerate() phase, 
+ *	In the dev_enumerate() phase,
  */
 
 void hardwaremain(int boot_complete);
@@ -56,19 +57,21 @@ void hardwaremain(int boot_complete);
 void hardwaremain(int boot_complete)
 {
 	struct lb_memory *lb_mem;
+	tsc_t timestamps[6];
 
-	post_code(0x80);
+	timestamps[0] = rdtsc();
+	post_code(POST_ENTRY_RAMSTAGE);
 
 	/* console_init() MUST PRECEDE ALL printk()! */
 	console_init();
-	
-	post_code(0x39);
 
-	printk(BIOS_NOTICE, "coreboot-%s%s %s %s...\n", 
+	post_code(POST_CONSOLE_READY);
+
+	printk(BIOS_NOTICE, "coreboot-%s%s %s %s...\n",
 		      coreboot_version, coreboot_extra_version, coreboot_build,
 		      (boot_complete)?"rebooting":"booting");
 
-	post_code(0x40);
+	post_code(POST_CONSOLE_BOOT_MSG);
 
 	/* If we have already booted attempt a hard reboot */
 	if (boot_complete) {
@@ -76,32 +79,53 @@ void hardwaremain(int boot_complete)
 	}
 
 	/* FIXME: Is there a better way to handle this? */
-	init_timer(); 
+	init_timer();
 
+	timestamps[1] = rdtsc();
 	/* Find the devices we don't have hard coded knowledge about. */
 	dev_enumerate();
-	post_code(0x66);
+	post_code(POST_DEVICE_ENUMERATION_COMPLETE);
+
+	timestamps[2] = rdtsc();
 	/* Now compute and assign the bus resources. */
 	dev_configure();
-	post_code(0x88);
+	post_code(POST_DEVICE_CONFIGURATION_COMPLETE);
+
+	timestamps[3] = rdtsc();
 	/* Now actually enable devices on the bus */
 	dev_enable();
+
+	timestamps[4] = rdtsc();
 	/* And of course initialize devices on the bus */
 	dev_initialize();
-	post_code(0x89);
+	post_code(POST_DEVICES_ENABLED);
 
+	timestamps[5] = rdtsc();
 #if CONFIG_WRITE_HIGH_TABLES == 1
 	cbmem_initialize();
+#if CONFIG_CONSOLE_CBMEM
+	cbmemc_reinit();
+#endif
 #endif
 #if CONFIG_HAVE_ACPI_RESUME == 1
 	suspend_resume();
 	post_code(0x8a);
 #endif
 
+	timestamp_add(TS_START_RAMSTAGE, timestamps[0]);
+	timestamp_add(TS_DEVICE_ENUMERATE, timestamps[1]);
+	timestamp_add(TS_DEVICE_CONFIGURE, timestamps[2]);
+	timestamp_add(TS_DEVICE_ENABLE, timestamps[3]);
+	timestamp_add(TS_DEVICE_INITIALIZE, timestamps[4]);
+	timestamp_add(TS_DEVICE_DONE, timestamps[5]);
+	timestamp_add_now(TS_WRITE_TABLES);
+
 	/* Now that we have collected all of our information
 	 * write our configuration tables.
 	 */
 	lb_mem = write_tables();
+
+	timestamp_add_now(TS_LOAD_PAYLOAD);
 	cbfs_load_payload(lb_mem, CONFIG_CBFS_PREFIX "/payload");
 	printk(BIOS_ERR, "Boot failed.\n");
 }