X-Git-Url: http://wien.tomnetworks.com/gitweb/?a=blobdiff_plain;f=src%2Fbeh_uart_rx_tb.vhd;fp=src%2Fbeh_uart_rx_tb.vhd;h=26adbda22b46f13419dc05fe61530b19af389af3;hb=7ab4feea3c78c90283cf2131cc31f0149e94ea85;hp=bca920a315295223640309942b87543f8f2fceeb;hpb=e0d31dc4d01eb9184ef9c1f8d16fadbae8e891d7;p=hwmod.git

diff --git a/src/beh_uart_rx_tb.vhd b/src/beh_uart_rx_tb.vhd
index bca920a..26adbda 100644
--- a/src/beh_uart_rx_tb.vhd
+++ b/src/beh_uart_rx_tb.vhd
@@ -7,51 +7,83 @@ entity beh_uart_rx_tb is
 end entity beh_uart_rx_tb;
 
 architecture sim of beh_uart_rx_tb is
+	constant CLK_FREQ : integer := 33000000;
+	constant BAUDRATE : integer := 115200;
+	constant BAUD : integer := CLK_FREQ/BAUDRATE;
 
-	constant clk_period : time := 2ns;
-	signal clock : std_logic;
-	signal reset : std_logic;
-	signal done : std_logic;
-	signal newsig : std_logic;
-	signal data : std_logic_vector(7 downto 0);
-	signal serial_in: std_logic;
+	signal sys_clk, sys_res_n, rxd, rx_new : std_logic;
+	signal rx_data : std_logic_vector (7 downto 0);
+	signal stop : boolean := false;
 begin
 	inst : entity work.uart_rx(beh)
+	generic map (
+		CLK_FREQ => CLK_FREQ,
+		BAUDRATE => BAUDRATE
+	)
 	port map (
-		sys_clk => clock,
-		sys_res => reset,
-		txd => serial_in,
-		tx_data => data,
-		tx_new => newsig
+		sys_clk => sys_clk,
+		sys_res_n => sys_res_n,
+		rxd => rxd,
+		rx_data => rx_data,
+		rx_new => rx_new
 	);
 
-	stimuli : process
+	process
 	begin
-		serial_in <= '0';
-		wait for 10ns;
-		--send 'Hallo Welt'
-		serial_in <= '1';
-		wait for clk_period;
-		serial_in <= '0';
-		wait for 1000ns;
-
-		assert false report "Test finished" severity failure;
-	end process stimuli;
-
-	res_gen : process
-	begin
-		reset <= '0';
-		wait for 20ns;
-		reset <= '1';
-		wait for 1000ns;
-	end process res_gen;
+		sys_clk <= '0';
+		wait for 15 ns;
+		sys_clk <= '1';
+		wait for 15 ns;
+		if stop = true then
+			wait;
+		end if;
+	end process;
+
+	process
+		procedure exec_tc(testnr : integer;
+			constant testvector : std_logic_vector(9 downto 0);
+			constant expectedresult : std_logic_vector(7 downto 0)) is
+		begin
+			-- vorher auf high setzen um falling edge simulieren zu koennen
+			rxd <= '1';
+			icwait(sys_clk, 2);
 
-	clock_gen : process
+			for i in 0 to 9 loop
+				rxd <= testvector(9-i);
+				if i /= 9 then
+					icwait(sys_clk, BAUD);
+				end if;
+			end loop;
+		
+			wait until rx_new = '1';
+			if expectedresult = rx_data then
+				report "testfall " & integer'image(testnr) & " war erfolgreich";
+			else
+				report "testfall " & integer'image(testnr) & " schlug fehl";
+			end if;
+			icwait(sys_clk, 3);
+		end;
+
+		variable testvector : std_logic_vector(9 downto 0);
+		variable expectedresult : std_logic_vector(7 downto 0);
 	begin
-		clock <= '0';
-		wait for clk_period/2;
-		clock <= '1';
-		wait for clk_period/2;
-	end process clock_gen;
+		sys_res_n <= '0';
+		rxd <= '1';
+		icwait(sys_clk, 10);
+		sys_res_n <= '1';
+		icwait(sys_clk, 2);
+
+		-- 1. parameter: testfallnummer
+		-- 2. parameter: STARTBIT (1 bit) - immer '0' | 8 DATENBITS | 1 STOPBIT - immer '1'
+		-- 3. parameter: byte das rauskommen soll
+		exec_tc(1, b"0000011111", b"00001111");
+		exec_tc(2, b"0101010101", b"10101010");
+		exec_tc(3, b"0110011001", b"11001100");
+		exec_tc(4, b"0001100111", b"00110011");
+		exec_tc(5, b"0010101011", b"01010101");
+		exec_tc(6, b"0100110111", b"10011011");
 
+		stop <= true;
+		wait;
+	end process;
 end sim;