X-Git-Url: http://wien.tomnetworks.com/gitweb/?a=blobdiff_plain;f=src%2Fbeh_pc_communication_tb.vhd;h=d2a693e017c6c688626255cfd54c6d244cfb026f;hb=b6503f8ccf6fb6d0e88e514a306e32d7a7c1a5d7;hp=c8620959a8d2ddf7903a3aee32b48ed30c66abd0;hpb=021eb0653bb6229cc9275cd8198ce03301f54a39;p=hwmod.git

diff --git a/src/beh_pc_communication_tb.vhd b/src/beh_pc_communication_tb.vhd
index c862095..d2a693e 100644
--- a/src/beh_pc_communication_tb.vhd
+++ b/src/beh_pc_communication_tb.vhd
@@ -6,35 +6,55 @@ use work.textmode_vga_component_pkg.all;
 use work.textmode_vga_pkg.all;
 use work.textmode_vga_platform_dependent_pkg.all;
 
+-- this is for test file io
+use std.textio.all;
+
 entity beh_pc_communication_tb is
 end entity beh_pc_communication_tb;
 
 architecture sim of beh_pc_communication_tb is
+		type byte_file_type is file of hbyte;
+		subtype my_string is string(1 to 720);
+		signal sys_clk : std_logic;
+		signal sys_res_n : std_logic;
+		signal btn_a : std_logic;
+		signal tx_new : std_logic;
+		signal tx_done : std_logic;
+		signal rx_new : std_logic;
+		signal pc_get : std_logic;
+		signal pc_done : std_logic;
+		signal pc_busy : std_logic;
+		signal rx_data, tx_data : std_logic_vector(7 downto 0);
+
+		signal pc_zeile : hzeile;
+		signal pc_spalte : hspalte;
+		signal pc_char : hbyte;
 begin
-	-- display
+	-- pc_communication
 	inst : entity work.pc_communication(beh)
 	port map (
 		sys_clk => sys_clk,
 		sys_res_n => sys_res_n,
 
-		--button=> ,
+		--button
 		btn_a => btn_a,
 
-		--uart_tx=> ,
+		--uart_tx
 		tx_data => tx_data,
 		tx_new => tx_new,
 		tx_done => tx_done,
 
-		--uart_rx=> ,
+		--uart_rx
 		rx_data => rx_data,
 		rx_new => rx_new,
 
-		-- History=> ,
-		d_zeile => d_zeile,
-		d_spalte => d_spalte,
-		d_get => d_get,
-		d_done => d_done,
-		d_char => d_char--,
+		-- History
+		pc_zeile => pc_zeile,
+		pc_spalte => pc_spalte,
+		pc_get => pc_get,
+		pc_done => pc_done,
+		pc_busy => pc_busy,
+		pc_char => pc_char
 	);
 
 	clk : process
@@ -43,30 +63,74 @@ begin
 		wait for 15 ns;
 		sys_clk <= '1';
 		wait for 15 ns;
-		if stop = true then
-			wait;
-		end if;
 	end process clk;
 
-	stub_history process (d_get)
+	stub_history : process
 		file f : text open read_mode is "../../src/pc_communication.test";
+		variable rb : character;
+		variable good : boolean;
+		variable i : integer;
+		variable buf : my_string;
+		variable l : line;
 	begin
-		if rising_edge(d_get) then
-			read(f, d_char);
-			wait 30 ns;
-			done <= d_done;
-		end if;
+		pc_char <= (others => '0');
+		pc_done <= '0';
+		pc_busy <= '0';
+		wait until sys_res_n = '1';
+
+		while not endfile (f) loop
+			readline(f, l);
+			buf := l.all;
+			i := 1;
+			while i < l'length loop
+				pc_done <= '0';
+				wait until rising_edge(pc_get);
+				wait for 150 ns;
+				pc_char <= (others => '0');
+				pc_busy <= '1';
+				wait for 30 ns;
+				pc_char <= hbyte(std_logic_vector(to_unsigned(character'pos(buf(i)),8)));
+				i := i + 1;
+				pc_busy <= '0';
+				pc_done <= '1';
+				wait for 30 ns;
+			end loop;
+		end loop;
+
+		assert not endfile(f) report "test beendet" severity failure;
 	end process stub_history;
 
-	process
+	stub_uart : process
+	begin
+		tx_done <= '0';
+		wait until sys_res_n = '1';
+		while true loop
+			tx_done <= '0';
+			wait until rising_edge(tx_new);
+			wait for 300 ns;
+			tx_done <= '1';
+			wait for 30 ns;
+		end loop;
+	end process stub_uart;
+
+	reset_and_button : process
 	begin
 		-- init & reset
 		-- we only simulate pressing of button a by now!
-		sys_res_n <= 0;
-		wait for 100 ns;
-		sys_res_n <= 1;
-
-		btn_a <= 1;
+		sys_res_n <= '0';
+		btn_a <= '1';
+		rx_data <= ( others => '0');
+		rx_new <= '0';
+		
+		wait for 90 ns;
+		sys_res_n <= '1';
+		wait for 30 ns;
+		btn_a <= '0';
+		wait for 30 ns;
+		btn_a <= '1';
 		wait;
-	end process;
+		--wait for 1000 ns;
+		--assert false report "test beendet" severity failure;
+	end process reset_and_button;
+
 end architecture sim;