X-Git-Url: http://wien.tomnetworks.com/gitweb/?a=blobdiff_plain;f=src%2Fbeh_history_tb.vhd;h=f249361c03d3f9869e405015187fe99d630ecb42;hb=51361c5dc1ab06332a04260f5192adcb398238e6;hp=d05236adfb851ffea9e8a69b8c1b52fea164301f;hpb=c4835e02b7f9b0d71547aec609667b7b5aed75ce;p=hwmod.git

diff --git a/src/beh_history_tb.vhd b/src/beh_history_tb.vhd
index d05236a..f249361 100644
--- a/src/beh_history_tb.vhd
+++ b/src/beh_history_tb.vhd
@@ -46,17 +46,13 @@ architecture sim of beh_history_tb is
 	signal pc_spalte : hspalte;
 	signal pc_get, pc_done : std_logic;
 	signal pc_char : hbyte;
-	signal pc_busy : std_logic;
 	--dummy button
 	signal btn_a_int : std_logic;
 
-	--output beautifier
-	signal tx_debug : character;
-
 	signal stop : boolean := false;
 begin
 	-- history
-	inst : entity work.history(beh)
+	inst : history
 	port map (
 		sys_clk => sys_clk,
 		sys_res_n => sys_res_n,
@@ -87,12 +83,11 @@ begin
 		pc_spalte => pc_spalte,
 		pc_zeile  => pc_zeile,
 		pc_char   => pc_char,
-		pc_busy   => pc_busy,
 		pc_done   => pc_done
 	);
 
 	-- display
-	inst_disp : entity work.display(beh)
+	inst_disp : display
 	port map (
 		sys_clk => sys_clk,
 		sys_res_n => sys_res_n,
@@ -112,7 +107,7 @@ begin
 	);
 
 	-- parser
-	inst_parser : entity work.parser(beh)
+	inst_parser : parser
 	port map (
 		sys_clk => sys_clk,
 		sys_res_n => sys_res_n,
@@ -130,7 +125,7 @@ begin
 	);
 
 	-- scanner
-	inst_scan : entity work.scanner(beh)
+	inst_scan : scanner
 	port map (
 		sys_clk => sys_clk,
 		sys_res_n => sys_res_n,
@@ -147,7 +142,7 @@ begin
 		finished => finished
 	);
 	--uart_tx
-	inst_uart : entity work.uart_tx(beh)
+	inst_uart : uart_tx
 	port map (
 		sys_clk => sys_clk,
 		sys_res_n => sys_res_n,
@@ -158,7 +153,7 @@ begin
 	);
 
 	--pc_communication
-	inst_pc_com : entity work.pc_communication(beh)
+	inst_pc_com : pc_communication
 	port map(
 		sys_clk => sys_clk,
 		sys_res_n => sys_res_n,
@@ -176,10 +171,8 @@ begin
 		pc_spalte => pc_spalte,
 		pc_get    => pc_get,
 		pc_done   => pc_done,
-		pc_char   => pc_char,
-		pc_busy   => pc_busy
+		pc_char   => pc_char
 	);
-	tx_debug <= character'val(to_integer(unsigned(tx_data)));
 
 	process
 	begin
@@ -310,7 +303,8 @@ begin
 			report "==================";
 		end loop f_loop;
 
-		icwait(sys_clk, 850);
+		-- uart ist ziemlich langsam...
+		icwait(sys_clk, 1000000000);
 		stop <= true;
 		wait;
 	end process;
@@ -319,7 +313,7 @@ begin
 	begin
 		btn_a_int <= '1';
 		wait until sys_res_n = '1';
-		wait for 50000 * 15 ns;
+		icwait(sys_clk, 50000);
 		wait until rising_edge(sys_clk);
 		btn_a_int <= '0';
 		wait for 30 ns;