X-Git-Url: http://wien.tomnetworks.com/gitweb/?a=blobdiff_plain;f=src%2FKconfig;h=c165d932a7ee444fe3347567f5dc58e7533ad7d2;hb=aff6dc21499295fedae35e52bc906a22831df323;hp=9153ca0675ebcb046ed819b1f9fcad7cc848b622;hpb=5015f79857738c47d98b01446eb0e248ba835f5a;p=coreboot.git diff --git a/src/Kconfig b/src/Kconfig index 9153ca067..c165d932a 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -87,7 +87,7 @@ config SCONFIG_GENPARSER help Enable this option if you are working on the sconfig device tree parser and made changes to sconfig.l and - sconfig.y. + sconfig.y. Otherwise, say N. config USE_OPTION_TABLE @@ -98,10 +98,33 @@ config USE_OPTION_TABLE Enable this option if coreboot shall read options from the "CMOS" NVRAM instead of using hard coded values. +config COMPRESS_RAMSTAGE + bool "Compress ramstage with LZMA" + default y + help + Compress ramstage to save memory in the flash image. Note + that decompression might slow down booting if the boot flash + is connected through a slow Link (i.e. SPI) + +config INCLUDE_CONFIG_FILE + bool "Include the coreboot config file into the ROM image" + default y + help + Include in CBFS the coreboot config file that was used to compile the ROM image + endmenu source src/mainboard/Kconfig -source src/arch/i386/Kconfig + +# This option is used to set the architecture of a mainboard to X86. +# It is usually set in mainboard/*/Kconfig. +config ARCH_X86 + bool + default n + +if ARCH_X86 +source src/arch/x86/Kconfig +endif menu "Chipset" @@ -115,6 +138,8 @@ comment "Super I/O" source src/superio/Kconfig comment "Devices" source src/devices/Kconfig +comment "Embedded Controllers" +source src/ec/Kconfig endmenu @@ -126,22 +151,6 @@ config PCI_BUS_SEGN_BITS int default 0 -config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID - hex - default 0x0 - -config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID - hex - default 0x0 - -config CPU_ADDR_BITS - int - default 36 - -config LOGICAL_CPUS - bool - default y - config PCI_ROM_RUN bool default n @@ -162,10 +171,16 @@ config MMCONF_SUPPORT bool default n -config ATI_RAGE_XL +source src/console/Kconfig + +# This should default to N and be set by SuperI/O drivers that have an UART +config HAVE_UART_IO_MAPPED bool + default y -source src/console/Kconfig +config HAVE_UART_MEMORY_MAPPED + bool + default n config HAVE_ACPI_RESUME bool @@ -289,6 +304,10 @@ config GENERATE_PIRQ_TABLE bool default HAVE_PIRQ_TABLE +config GENERATE_SMBIOS_TABLES + bool + default y + menu "System tables" config WRITE_HIGH_TABLES @@ -327,13 +346,23 @@ config GENERATE_PIRQ_TABLE If unsure, say Y. +config GENERATE_SMBIOS_TABLES + depends on ARCH_X86 + bool "Generate SMBIOS tables" + default y + help + Generate SMBIOS tables for this board. + + If unsure, say Y. + endmenu menu "Payload" choice prompt "Add a payload" - default PAYLOAD_NONE + default PAYLOAD_NONE if !ARCH_X86 + default PAYLOAD_SEABIOS if ARCH_X86 config PAYLOAD_NONE bool "None" @@ -355,20 +384,77 @@ config PAYLOAD_ELF You will be able to specify the location and file name of the payload image later. +config PAYLOAD_SEABIOS + bool "SeaBIOS" + depends on ARCH_X86 + help + Select this option if you want to build a coreboot image + with a SeaBIOS payload. If you don't know what this is + about, just leave it enabled. + + See http://coreboot.org/Payloads for more information. + +config PAYLOAD_FILO + bool "FILO" + help + Select this option if you want to build a coreboot image + with a FILO payload. If you don't know what this is + about, just leave it enabled. + + See http://coreboot.org/Payloads for more information. + +endchoice + +choice + prompt "SeaBIOS version" + default SEABIOS_STABLE + depends on PAYLOAD_SEABIOS + +config SEABIOS_STABLE + bool "stable" + help + Stable SeaBIOS version +config SEABIOS_MASTER + bool "master" + help + Newest SeaBIOS version +endchoice + +choice + prompt "FILO version" + default FILO_STABLE + depends on PAYLOAD_FILO + +config FILO_STABLE + bool "0.6.0" + help + Stable FILO version +config FILO_MASTER + bool "HEAD" + help + Newest FILO version endchoice -config FALLBACK_PAYLOAD_FILE +config PAYLOAD_FILE string "Payload path and filename" depends on PAYLOAD_ELF default "payload.elf" help The path and filename of the ELF executable file to use as payload. +config PAYLOAD_FILE + depends on PAYLOAD_SEABIOS + default "$(obj)/seabios/out/bios.bin.elf" + +config PAYLOAD_FILE + depends on PAYLOAD_FILO + default "payloads/external/FILO/filo/build/filo.elf" + # TODO: Defined if no payload? Breaks build? config COMPRESSED_PAYLOAD_LZMA bool "Use LZMA compression for payloads" default y - depends on PAYLOAD_ELF + depends on PAYLOAD_ELF || PAYLOAD_SEABIOS || PAYLOAD_FILO help In order to reduce the size payloads take up in the ROM chip coreboot can compress them using the LZMA algorithm. @@ -390,14 +476,14 @@ config VGA_BIOS You will be able to specify the location and file name of the image later. -config FALLBACK_VGA_BIOS_FILE +config VGA_BIOS_FILE string "VGA BIOS path and filename" depends on VGA_BIOS default "vgabios.bin" help The path and filename of the file to use as VGA BIOS. -config FALLBACK_VGA_BIOS_ID +config VGA_BIOS_ID string "VGA device PCI IDs" depends on VGA_BIOS default "1106,3230" @@ -421,7 +507,7 @@ config INTEL_MBI You will be able to specify the location and file name of the image later. -config FALLBACK_MBI_FILE +config MBI_FILE string "Intel MBI path and filename" depends on INTEL_MBI default "mbi.bin" @@ -430,40 +516,31 @@ config FALLBACK_MBI_FILE endmenu -menu "Bootsplash" - depends on PCI_OPTION_ROM_RUN_YABEL +menu "Display" + depends on PCI_OPTION_ROM_RUN_YABEL || PCI_OPTION_ROM_RUN_REALMODE -config BOOTSPLASH - prompt "Show graphical bootsplash" +config FRAMEBUFFER_SET_VESA_MODE + prompt "Set VESA framebuffer mode" bool - depends on PCI_OPTION_ROM_RUN_YABEL + depends on PCI_OPTION_ROM_RUN_YABEL || PCI_OPTION_ROM_RUN_REALMODE help - This option shows a graphical bootsplash screen. The grapics are - loaded from the CBFS file bootsplash.jpg. - -config FALLBACK_BOOTSPLASH_FILE - string "Bootsplash path and filename" - depends on BOOTSPLASH - default "bootsplash.jpg" - help - The path and filename of the file to use as graphical bootsplash - screen. The file format has to be jpg. + Set VESA framebuffer mode (needed for bootsplash) # TODO: Turn this into a "choice". config FRAMEBUFFER_VESA_MODE prompt "VESA framebuffer video mode" hex default 0x117 - depends on BOOTSPLASH + depends on FRAMEBUFFER_SET_VESA_MODE help - This option sets the resolution used for the coreboot framebuffer and - bootsplash screen. Set to 0x117 for 1024x768x16. A diligent soul will + This option sets the resolution used for the coreboot framebuffer (and + bootsplash screen). Set to 0x117 for 1024x768x16. A diligent soul will some day make this a "choice". -config COREBOOT_KEEP_FRAMEBUFFER +config FRAMEBUFFER_KEEP_VESA_MODE prompt "Keep VESA framebuffer" bool - depends on BOOTSPLASH + depends on PCI_OPTION_ROM_RUN_YABEL || PCI_OPTION_ROM_RUN_REALMODE help This option keeps the framebuffer mode set after coreboot finishes execution. If this option is enabled, coreboot will pass a @@ -471,6 +548,21 @@ config COREBOOT_KEEP_FRAMEBUFFER framebuffer driver. If this option is disabled, coreboot will switch back to text mode before handing control to a payload. +config BOOTSPLASH + prompt "Show graphical bootsplash" + bool + depends on FRAMEBUFFER_SET_VESA_MODE + help + This option shows a graphical bootsplash screen. The grapics are + loaded from the CBFS file bootsplash.jpg. + +config BOOTSPLASH_FILE + string "Bootsplash path and filename" + depends on BOOTSPLASH + default "bootsplash.jpg" + help + The path and filename of the file to use as graphical bootsplash + screen. The file format has to be jpg. endmenu menu "Debugging" @@ -481,7 +573,7 @@ config GDB_STUB default y help If enabled, you will be able to set breakpoints for gdb debugging. - See src/arch/i386/lib/c_start.S for details. + See src/arch/x86/lib/c_start.S for details. config HAVE_DEBUG_RAM_SETUP def_bool n @@ -578,6 +670,23 @@ config DEBUG_MALLOC If unsure, say N. endif +config DEBUG_ACPI + def_bool n + +# Only visible if debug level is DEBUG (7) or SPEW (8) as it does additional +# printk(BIOS_DEBUG, ...) calls. +if DEFAULT_CONSOLE_LOGLEVEL_7 || DEFAULT_CONSOLE_LOGLEVEL_8 +config DEBUG_ACPI + bool "Output verbose ACPI debug messages" + default n + help + This option enables additional ACPI related debug messages. + + Note: This option will slightly increase the size of the coreboot image. + + If unsure, say N. +endif + config REALMODE_DEBUG def_bool n depends on PCI_OPTION_ROM_RUN_REALMODE @@ -740,8 +849,17 @@ config LLSHELL help If enabled, you will have a low level shell to examine your machine. Put llshell() in your (romstage) code to start the shell. - See src/arch/i386/llshell/llshell.inc for details. + See src/arch/x86/llshell/llshell.inc for details. +config TRACE + bool "Trace function calls" + default n + help + If enabled, every function will print information to console once + the function is entered. The syntax is ~0xaaaabbbb(0xccccdddd) + the 0xaaaabbbb is the actual function and 0xccccdddd is EIP + of calling function. Please note some printk releated functions + are omitted from trace to have good looking console dumps. endmenu config LIFT_BSP_APIC_ID @@ -765,10 +883,6 @@ config WARNINGS_ARE_ERRORS bool default y -config ID_SECTION_OFFSET - hex - default 0x10 - # The four POWER_BUTTON_DEFAULT_ENABLE, POWER_BUTTON_DEFAULT_DISABLE, # POWER_BUTTON_FORCE_ENABLE and POWER_BUTTON_FORCE_DISABLE options are # mutually exclusive. One of these options must be selected in the