X-Git-Url: http://wien.tomnetworks.com/gitweb/?a=blobdiff_plain;f=src%2FKconfig;h=b9539d1a1e976178783ad3f124cbd1dcf45e097a;hb=e50952f53294b3939f851c0feacaf13e31bc5a44;hp=461087d170ec2ac87ca7f838cbe253ae57a69f68;hpb=6f57b514cb6e0598b295a3d8a4345dd42209e1e6;p=coreboot.git

diff --git a/src/Kconfig b/src/Kconfig
index 461087d17..b9539d1a1 100644
--- a/src/Kconfig
+++ b/src/Kconfig
@@ -80,6 +80,16 @@ config CCACHE
 	  Enables the use of ccache for faster builds.
 	  Requires ccache in path.
 
+config SCONFIG_GENPARSER
+	bool "Generate SCONFIG parser using flex and bison"
+	default n
+	depends on EXPERT
+	help
+	  Enable this option if you are working on the sconfig
+	  device tree parser and made changes to sconfig.l and
+	  sconfig.y. 
+	  Otherwise, say N.
+
 config USE_OPTION_TABLE
 	bool "Use CMOS for configuration values"
 	default n
@@ -91,7 +101,16 @@ config USE_OPTION_TABLE
 endmenu
 
 source src/mainboard/Kconfig
-source src/arch/i386/Kconfig
+
+# This option is used to set the architecture of a mainboard to X86.
+# It is usually set in mainboard/*/Kconfig.
+config ARCH_X86
+	bool
+	default n
+
+if ARCH_X86
+source src/arch/x86/Kconfig
+endif
 
 menu "Chipset"
 
@@ -105,6 +124,8 @@ comment "Super I/O"
 source src/superio/Kconfig
 comment "Devices"
 source src/devices/Kconfig
+comment "Embedded Controllers"
+source src/ec/Kconfig
 
 endmenu
 
@@ -116,22 +137,6 @@ config PCI_BUS_SEGN_BITS
 	int
 	default 0
 
-config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-	hex
-	default 0x0
-
-config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-	hex
-	default 0x0
-
-config CPU_ADDR_BITS
-	int
-	default 36
-
-config LOGICAL_CPUS
-	bool
-	default y
-
 config PCI_ROM_RUN
 	bool
 	default n
@@ -140,10 +145,6 @@ config HEAP_SIZE
 	hex
 	default 0x4000
 
-config USE_PRINTK_IN_CAR
-	bool
-	default n
-
 config MAX_CPUS
 	int
 	default 1
@@ -156,9 +157,6 @@ config MMCONF_SUPPORT
 	bool
 	default n
 
-config ATI_RAGE_XL
-	bool
-
 source src/console/Kconfig
 
 config HAVE_ACPI_RESUME
@@ -244,27 +242,6 @@ config GFXUMA
 #
 # endmenu
 
-#TODO Remove this option or make it useful.
-config HAVE_LOW_TABLES
-	bool
-	default y
-	help
-	  This Option is unused in the code.  Since two boards try to set it to
-	  'n', they may be broken.  We either need to make the option useful or
-	  get rid of it.  The broken boards are:
-	  asus/m2v-mx_se
-	  supermicro/h8dme
-
-config HAVE_HIGH_TABLES
-	bool
-	default y
-	help
-	  This variable specifies whether a given northbridge has high table
-	  support.
-	  It is set in northbridge/*/Kconfig.
-	  Whether or not the high tables are actually written by coreboot is
-	  configurable by the user via WRITE_HIGH_TABLES.
-
 config HAVE_ACPI_TABLES
 	bool
 	help
@@ -304,15 +281,10 @@ config GENERATE_PIRQ_TABLE
 	bool
 	default HAVE_PIRQ_TABLE
 
-config WRITE_HIGH_TABLES
-	bool
-	default HAVE_HIGH_TABLES
-
 menu "System tables"
 
 config WRITE_HIGH_TABLES
 	bool "Write 'high' tables to avoid being overwritten in F segment"
-	depends on HAVE_HIGH_TABLES
 	default y
 
 config MULTIBOOT
@@ -353,7 +325,8 @@ menu "Payload"
 
 choice
 	prompt "Add a payload"
-	default PAYLOAD_NONE
+	default PAYLOAD_NONE if !ARCH_X86
+	default PAYLOAD_SEABIOS if ARCH_X86
 
 config PAYLOAD_NONE
 	bool "None"
@@ -375,20 +348,77 @@ config PAYLOAD_ELF
 	  You will be able to specify the location and file name of the
 	  payload image later.
 
+config PAYLOAD_SEABIOS
+	bool "SeaBIOS"
+	depends on ARCH_X86
+	help
+	  Select this option if you want to build a coreboot image
+	  with a SeaBIOS payload. If you don't know what this is
+	  about, just leave it enabled.
+
+	  See http://coreboot.org/Payloads for more information.
+
+config PAYLOAD_FILO
+	bool "FILO"
+	help
+	  Select this option if you want to build a coreboot image
+	  with a FILO payload. If you don't know what this is
+	  about, just leave it enabled.
+
+	  See http://coreboot.org/Payloads for more information.
+
+endchoice
+
+choice
+	prompt "SeaBIOS version"
+	default SEABIOS_STABLE
+	depends on PAYLOAD_SEABIOS
+
+config SEABIOS_STABLE
+	bool "stable"
+	help
+	  Stable SeaBIOS version
+config SEABIOS_MASTER
+	bool "master"
+	help
+	  Newest SeaBIOS version
+endchoice
+
+choice
+	prompt "FILO version"
+	default FILO_STABLE
+	depends on PAYLOAD_FILO
+
+config FILO_STABLE
+	bool "0.6.0"
+	help
+	  Stable FILO version
+config FILO_MASTER
+	bool "HEAD"
+	help
+	  Newest FILO version
 endchoice
 
-config FALLBACK_PAYLOAD_FILE
+config PAYLOAD_FILE
 	string "Payload path and filename"
 	depends on PAYLOAD_ELF
 	default "payload.elf"
 	help
 	  The path and filename of the ELF executable file to use as payload.
 
+config PAYLOAD_FILE
+	depends on PAYLOAD_SEABIOS
+	default "payloads/external/SeaBIOS/seabios/out/bios.bin.elf"
+
+config PAYLOAD_FILE
+	depends on PAYLOAD_FILO
+	default "payloads/external/FILO/filo/build/filo.elf"
+
 # TODO: Defined if no payload? Breaks build?
 config COMPRESSED_PAYLOAD_LZMA
 	bool "Use LZMA compression for payloads"
 	default y
-	depends on PAYLOAD_ELF
+	depends on PAYLOAD_ELF || PAYLOAD_SEABIOS || PAYLOAD_FILO
 	help
 	  In order to reduce the size payloads take up in the ROM chip
 	  coreboot can compress them using the LZMA algorithm.
@@ -410,14 +440,14 @@ config VGA_BIOS
 	  You will be able to specify the location and file name of the
 	  image later.
 
-config FALLBACK_VGA_BIOS_FILE
+config VGA_BIOS_FILE
 	string "VGA BIOS path and filename"
 	depends on VGA_BIOS
 	default "vgabios.bin"
 	help
 	  The path and filename of the file to use as VGA BIOS.
 
-config FALLBACK_VGA_BIOS_ID
+config VGA_BIOS_ID
 	string "VGA device PCI IDs"
 	depends on VGA_BIOS
 	default "1106,3230"
@@ -441,7 +471,7 @@ config INTEL_MBI
 	  You will be able to specify the location and file name of the
 	  image later.
 
-config FALLBACK_MBI_FILE
+config MBI_FILE
 	string "Intel MBI path and filename"
 	depends on INTEL_MBI
 	default "mbi.bin"
@@ -461,7 +491,7 @@ config BOOTSPLASH
 	  This option shows a graphical bootsplash screen. The grapics are
 	  loaded from the CBFS file bootsplash.jpg.
 
-config FALLBACK_BOOTSPLASH_FILE
+config BOOTSPLASH_FILE
 	string "Bootsplash path and filename"
 	depends on BOOTSPLASH
 	default "bootsplash.jpg"
@@ -501,21 +531,15 @@ config GDB_STUB
 	default y
 	help
 	  If enabled, you will be able to set breakpoints for gdb debugging.
-	  See src/arch/i386/lib/c_start.S for details.
+	  See src/arch/x86/lib/c_start.S for details.
+
+config HAVE_DEBUG_RAM_SETUP
+	def_bool n
 
 config DEBUG_RAM_SETUP
 	bool "Output verbose RAM init debug messages"
 	default n
-	depends on (NORTHBRIDGE_AMD_AMDFAM10 \
-		 || NORTHBRIDGE_AMD_AMDK8 \
-		 || NORTHBRIDGE_VIA_CN700 \
-		 || NORTHBRIDGE_VIA_CX700 \
-		 || NORTHBRIDGE_VIA_VX800 \
-		 || NORTHBRIDGE_INTEL_E7501 \
-		 || NORTHBRIDGE_INTEL_I440BX \
-		 || NORTHBRIDGE_INTEL_I82810 \
-		 || NORTHBRIDGE_INTEL_I82830 \
-		 || NORTHBRIDGE_INTEL_I945)
+	depends on HAVE_DEBUG_RAM_SETUP
 	help
 	  This option enables additional RAM init related debug messages.
 	  It is recommended to enable this when debugging issues on your
@@ -525,6 +549,24 @@ config DEBUG_RAM_SETUP
 
 	  If unsure, say N.
 
+config HAVE_DEBUG_CAR
+	def_bool n
+
+config DEBUG_CAR
+	def_bool n
+	depends on HAVE_DEBUG_CAR
+
+if DEFAULT_CONSOLE_LOGLEVEL_7 || DEFAULT_CONSOLE_LOGLEVEL_8
+# Only visible if debug level is DEBUG (7) or SPEW (8) as it does additional
+# printk(BIOS_DEBUG, ...) calls.
+config DEBUG_CAR
+	bool "Output verbose Cache-as-RAM debug messages"
+	default n
+	depends on HAVE_DEBUG_CAR
+	help
+	  This option enables additional CAR related debug messages.
+endif
+
 config DEBUG_PIRQ
 	bool "Check PIRQ table consistency"
 	default n
@@ -532,16 +574,13 @@ config DEBUG_PIRQ
 	help
 	  If unsure, say N.
 
+config HAVE_DEBUG_SMBUS
+	def_bool n
+
 config DEBUG_SMBUS
 	bool "Output verbose SMBus debug messages"
 	default n
-	depends on (SOUTHBRIDGE_VIA_VT8237R \
-		 || NORTHBRIDGE_VIA_VX800 \
-		 || NORTHBRIDGE_VIA_CX700 \
-		 || NORTHBRIDGE_AMD_AMDK8 \
-		 || NORTHBRIDGE_AMD_AMDFAM10 \
-		 || BOARD_LIPPERT_SPACERUNNER_LX \
-		 || SOUTHBRIDGE_VIA_VT8231)
+	depends on HAVE_DEBUG_SMBUS
 	help
 	  This option enables additional SMBus (and SPD) debug messages.
 
@@ -560,6 +599,54 @@ config DEBUG_SMI
 
 	  If unsure, say N.
 
+config DEBUG_SMM_RELOCATION
+	bool "Debug SMM relocation code"
+	default n
+	depends on HAVE_SMI_HANDLER
+	help
+	  This option enables additional SMM handler relocation related
+	  debug messages.
+
+	  Note: This option will increase the size of the coreboot image.
+
+	  If unsure, say N.
+
+config DEBUG_MALLOC
+	def_bool n
+
+# Only visible if debug level is DEBUG (7) or SPEW (8) as it does additional
+# printk(BIOS_DEBUG, ...) calls.
+if DEFAULT_CONSOLE_LOGLEVEL_7 || DEFAULT_CONSOLE_LOGLEVEL_8
+config DEBUG_MALLOC
+	bool "Output verbose malloc debug messages"
+	default n
+	help
+	  This option enables additional malloc related debug messages.
+
+	  Note: This option will increase the size of the coreboot image.
+
+	  If unsure, say N.
+endif
+
+config REALMODE_DEBUG
+	def_bool n
+	depends on PCI_OPTION_ROM_RUN_REALMODE
+
+if DEFAULT_CONSOLE_LOGLEVEL_7 || DEFAULT_CONSOLE_LOGLEVEL_8
+# Only visible if debug level is DEBUG (7) or SPEW (8) as it does additional
+# printk(BIOS_DEBUG, ...) calls.
+config REALMODE_DEBUG
+	bool "Enable debug messages for option ROM execution"
+	default n
+	depends on PCI_OPTION_ROM_RUN_REALMODE
+	help
+	  This option enables additional x86emu related debug messages.
+
+	  Note: This option will increase the time to emulate a ROM.
+
+	  If unsure, say N.
+endif
+
 config X86EMU_DEBUG
 	bool "Output verbose x86emu debug messages"
 	default n
@@ -703,7 +790,7 @@ config LLSHELL
 	help
 	  If enabled, you will have a low level shell to examine your machine.
 	  Put llshell() in your (romstage) code to start the shell.
-	  See src/arch/i386/llshell/llshell.inc for details.
+	  See src/arch/x86/llshell/llshell.inc for details.
 
 endmenu
 
@@ -716,6 +803,10 @@ config AP_CODE_IN_CAR
 	bool
 	default n
 
+config RAMINIT_SYSINFO
+	bool
+	default n
+
 config ENABLE_APIC_EXT_ID
 	bool
 	default n
@@ -728,4 +819,43 @@ config ID_SECTION_OFFSET
 	hex
 	default 0x10
 
+# The four POWER_BUTTON_DEFAULT_ENABLE, POWER_BUTTON_DEFAULT_DISABLE,
+# POWER_BUTTON_FORCE_ENABLE and POWER_BUTTON_FORCE_DISABLE options are
+# mutually exclusive. One of these options must be selected in the
+# mainboard Kconfig if the chipset supports enabling and disabling of
+# the power button. Chipset code uses the ENABLE_POWER_BUTTON option set
+# in mainboard/Kconfig to know if the button should be enabled or not.
+
+config POWER_BUTTON_DEFAULT_ENABLE
+	def_bool n
+	help
+	  Select when the board has a power button which can optionally be
+	  disabled by the user.
+
+config POWER_BUTTON_DEFAULT_DISABLE
+	def_bool n
+	help
+	  Select when the board has a power button which can optionally be
+	  enabled by the user, e.g. when the board ships with a jumper over
+	  the power switch contacts.
+
+config POWER_BUTTON_FORCE_ENABLE
+	def_bool n
+	help
+	  Select when the board requires that the power button is always
+	  enabled.
+
+config POWER_BUTTON_FORCE_DISABLE
+	def_bool n
+	help
+	  Select when the board requires that the power button is always
+	  disabled, e.g. when it has been hardwired to ground.
+
+config POWER_BUTTON_IS_OPTIONAL
+	bool
+	default y if POWER_BUTTON_DEFAULT_ENABLE || POWER_BUTTON_DEFAULT_DISABLE
+	default n if !(POWER_BUTTON_DEFAULT_ENABLE || POWER_BUTTON_DEFAULT_DISABLE)
+	help
+	  Internal option that controls ENABLE_POWER_BUTTON visibility.
+
 source src/Kconfig.deprecated_options