X-Git-Url: http://wien.tomnetworks.com/gitweb/?a=blobdiff_plain;f=src%2FKconfig;h=a61efe1a8e7025d0b88d1fb16b05975b12f136df;hb=77180546c84278f8e613aa912e432ee084425f88;hp=e4b4e0377a4b2c3dd176676083c0c1d7be7d18fc;hpb=f733d4754438f7289dd84d19871c7fe0a322801e;p=coreboot.git diff --git a/src/Kconfig b/src/Kconfig index e4b4e0377..a61efe1a8 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -80,6 +80,24 @@ config CCACHE Enables the use of ccache for faster builds. Requires ccache in path. +config SCONFIG_GENPARSER + bool "Generate SCONFIG parser using flex and bison" + default n + depends on EXPERT + help + Enable this option if you are working on the sconfig + device tree parser and made changes to sconfig.l and + sconfig.y. + Otherwise, say N. + +config USE_OPTION_TABLE + bool "Use CMOS for configuration values" + default n + depends on HAVE_OPTION_TABLE + help + Enable this option if coreboot shall read options from the "CMOS" + NVRAM instead of using hard coded values. + endmenu source src/mainboard/Kconfig @@ -90,96 +108,6 @@ menu "Chipset" comment "CPU" source src/cpu/Kconfig comment "Northbridge" - -menu "HyperTransport setup" - depends on (NORTHBRIDGE_AMD_AMDK8 || NORTHBRIDGE_AMD_AMDFAM10) && EXPERT - -choice - prompt "HyperTransport frequency" - default LIMIT_HT_SPEED_AUTO - help - This option sets the maximum permissible HyperTransport link - frequency. - - Use of this option will only limit the autodetected HT frequency. - It will not (and cannot) increase the frequency beyond the - autodetected limits. - - This is primarily used to work around poorly designed or laid out - HT traces on certain motherboards. - -config LIMIT_HT_SPEED_200 - bool "Limit HT frequency to 200MHz" -config LIMIT_HT_SPEED_400 - bool "Limit HT frequency to 400MHz" -config LIMIT_HT_SPEED_600 - bool "Limit HT frequency to 600MHz" -config LIMIT_HT_SPEED_800 - bool "Limit HT frequency to 800MHz" -config LIMIT_HT_SPEED_1000 - bool "Limit HT frequency to 1.0GHz" -config LIMIT_HT_SPEED_1200 - bool "Limit HT frequency to 1.2GHz" -config LIMIT_HT_SPEED_1400 - bool "Limit HT frequency to 1.4GHz" -config LIMIT_HT_SPEED_1600 - bool "Limit HT frequency to 1.6GHz" -config LIMIT_HT_SPEED_1800 - bool "Limit HT frequency to 1.8GHz" -config LIMIT_HT_SPEED_2000 - bool "Limit HT frequency to 2.0GHz" -config LIMIT_HT_SPEED_2200 - bool "Limit HT frequency to 2.2GHz" -config LIMIT_HT_SPEED_2400 - bool "Limit HT frequency to 2.4GHz" -config LIMIT_HT_SPEED_2600 - bool "Limit HT frequency to 2.6GHz" -config LIMIT_HT_SPEED_AUTO - bool "Autodetect HT frequency" -endchoice - -choice - prompt "HyperTransport downlink width" - default LIMIT_HT_DOWN_WIDTH_16 - help - This option sets the maximum permissible HyperTransport - downlink width. - - Use of this option will only limit the autodetected HT width. - It will not (and cannot) increase the width beyond the autodetected - limits. - - This is primarily used to work around poorly designed or laid out HT - traces on certain motherboards. - -config LIMIT_HT_DOWN_WIDTH_8 - bool "8 bits" -config LIMIT_HT_DOWN_WIDTH_16 - bool "16 bits" -endchoice - -choice - prompt "HyperTransport uplink width" - default LIMIT_HT_UP_WIDTH_16 - help - This option sets the maximum permissible HyperTransport - uplink width. - - Use of this option will only limit the autodetected HT width. - It will not (and cannot) increase the width beyond the autodetected - limits. - - This is primarily used to work around poorly designed or laid out HT - traces on certain motherboards. - -config LIMIT_HT_UP_WIDTH_8 - bool "8 bits" -config LIMIT_HT_UP_WIDTH_16 - bool "16 bits" -endchoice - -endmenu - source src/northbridge/Kconfig comment "Southbridge" source src/southbridge/Kconfig @@ -190,6 +118,10 @@ source src/devices/Kconfig endmenu +menu "Generic Drivers" +source src/drivers/Kconfig +endmenu + config PCI_BUS_SEGN_BITS int default 0 @@ -206,26 +138,6 @@ config CPU_ADDR_BITS int default 36 -config XIP_ROM_BASE - hex - default 0xfffe0000 - -config XIP_ROM_SIZE - hex - default 0x20000 - -config LB_CKS_RANGE_START - int - default 49 - -config LB_CKS_RANGE_END - int - default 125 - -config LB_CKS_LOC - int - default 126 - config LOGICAL_CPUS bool default y @@ -238,18 +150,6 @@ config HEAP_SIZE hex default 0x4000 -config DEBUG - bool - default n - -config USE_PRINTK_IN_CAR - bool - default n - -config USE_OPTION_TABLE - bool - default n - config MAX_CPUS int default 1 @@ -262,10 +162,6 @@ config MMCONF_SUPPORT bool default n -config RAMTOP - hex - default 0x200000 - config ATI_RAGE_XL bool @@ -275,6 +171,10 @@ config HAVE_ACPI_RESUME bool default n +config HAVE_ACPI_SLIC + bool + default n + config ACPI_SSDTX_NUM int default 0 @@ -296,13 +196,17 @@ config HAVE_MAINBOARD_RESOURCES bool default n +config USE_OPTION_TABLE + bool + default n + config HAVE_OPTION_TABLE bool - default y + default n help This variable specifies whether a given board has a cmos.layout file containing NVRAM/CMOS bit definitions. - It defaults to 'y' but can be changed to 'n' in mainboard/*/Kconfig. + It defaults to 'n' but can be selected in mainboard/*/Kconfig. config PIRQ_ROUTE bool @@ -346,27 +250,6 @@ config GFXUMA # # endmenu -#TODO Remove this option or make it useful. -config HAVE_LOW_TABLES - bool - default y - help - This Option is unused in the code. Since two boards try to set it to - 'n', they may be broken. We either need to make the option useful or - get rid of it. The broken boards are: - asus/m2v-mx_se - supermicro/h8dme - -config HAVE_HIGH_TABLES - bool - default y - help - This variable specifies whether a given northbridge has high table - support. - It is set in northbridge/*/Kconfig. - Whether or not the high tables are actually written by coreboot is - configurable by the user via WRITE_HIGH_TABLES. - config HAVE_ACPI_TABLES bool help @@ -406,15 +289,10 @@ config GENERATE_PIRQ_TABLE bool default HAVE_PIRQ_TABLE -config WRITE_HIGH_TABLES - bool - default HAVE_HIGH_TABLES - menu "System tables" config WRITE_HIGH_TABLES bool "Write 'high' tables to avoid being overwritten in F segment" - depends on HAVE_HIGH_TABLES default y config MULTIBOOT @@ -568,8 +446,8 @@ config FALLBACK_BOOTSPLASH_FILE depends on BOOTSPLASH default "bootsplash.jpg" help - The path and filename of the file to use as graphical bootsplash - screen. The file format has to be jpg. + The path and filename of the file to use as graphical bootsplash + screen. The file format has to be jpg. # TODO: Turn this into a "choice". config FRAMEBUFFER_VESA_MODE @@ -605,19 +483,13 @@ config GDB_STUB If enabled, you will be able to set breakpoints for gdb debugging. See src/arch/i386/lib/c_start.S for details. +config HAVE_DEBUG_RAM_SETUP + def_bool n + config DEBUG_RAM_SETUP bool "Output verbose RAM init debug messages" default n - depends on (NORTHBRIDGE_AMD_AMDFAM10 \ - || NORTHBRIDGE_AMD_AMDK8 \ - || NORTHBRIDGE_VIA_CN700 \ - || NORTHBRIDGE_VIA_CX700 \ - || NORTHBRIDGE_VIA_VX800 \ - || NORTHBRIDGE_INTEL_E7501 \ - || NORTHBRIDGE_INTEL_I440BX \ - || NORTHBRIDGE_INTEL_I82810 \ - || NORTHBRIDGE_INTEL_I82830 \ - || NORTHBRIDGE_INTEL_I945) + depends on HAVE_DEBUG_RAM_SETUP help This option enables additional RAM init related debug messages. It is recommended to enable this when debugging issues on your @@ -627,13 +499,30 @@ config DEBUG_RAM_SETUP If unsure, say N. +config HAVE_DEBUG_CAR + def_bool n + +config DEBUG_CAR + bool "Output verbose Cache-as-RAM debug messages" + default n + depends on HAVE_DEBUG_CAR + help + This option enables additional CAR related debug messages. + +config DEBUG_PIRQ + bool "Check PIRQ table consistency" + default n + depends on GENERATE_PIRQ_TABLE + help + If unsure, say N. + +config HAVE_DEBUG_SMBUS + def_bool n + config DEBUG_SMBUS bool "Output verbose SMBus debug messages" default n - depends on (SOUTHBRIDGE_VIA_VT8237R \ - || NORTHBRIDGE_VIA_VX800 \ - || NORTHBRIDGE_VIA_CX700 \ - || NORTHBRIDGE_AMD_AMDK8) + depends on HAVE_DEBUG_SMBUS help This option enables additional SMBus (and SPD) debug messages. @@ -652,6 +541,29 @@ config DEBUG_SMI If unsure, say N. +config DEBUG_SMM_RELOCATION + bool "Debug SMM relocation code" + default n + depends on HAVE_SMI_HANDLER + help + This option enables additional SMM handler relocation related + debug messages. + + Note: This option will increase the size of the coreboot image. + + If unsure, say N. + +config REALMODE_DEBUG + bool "Enable debug messages for option ROM execution" + default n + depends on PCI_OPTION_ROM_RUN_REALMODE + help + This option enables additional x86emu related debug messages. + + Note: This option will increase the time to emulate a ROM. + + If unsure, say N. + config X86EMU_DEBUG bool "Output verbose x86emu debug messages" default n @@ -680,7 +592,7 @@ config X86EMU_DEBUG_TRACE depends on X86EMU_DEBUG help Print _all_ opcodes that are executed by x86emu. - + WARNING: This will produce a LOT of output and take a long time. Note: This option will increase the size of the coreboot image. @@ -808,7 +720,7 @@ config AP_CODE_IN_CAR bool default n -config USE_INIT +config RAMINIT_SYSINFO bool default n @@ -818,10 +730,49 @@ config ENABLE_APIC_EXT_ID config WARNINGS_ARE_ERRORS bool - default n + default y config ID_SECTION_OFFSET hex default 0x10 +# The four POWER_BUTTON_DEFAULT_ENABLE, POWER_BUTTON_DEFAULT_DISABLE, +# POWER_BUTTON_FORCE_ENABLE and POWER_BUTTON_FORCE_DISABLE options are +# mutually exclusive. One of these options must be selected in the +# mainboard Kconfig if the chipset supports enabling and disabling of +# the power button. Chipset code uses the ENABLE_POWER_BUTTON option set +# in mainboard/Kconfig to know if the button should be enabled or not. + +config POWER_BUTTON_DEFAULT_ENABLE + def_bool n + help + Select when the board has a power button which can optionally be + disabled by the user. + +config POWER_BUTTON_DEFAULT_DISABLE + def_bool n + help + Select when the board has a power button which can optionally be + enabled by the user, e.g. when the board ships with a jumper over + the power switch contacts. + +config POWER_BUTTON_FORCE_ENABLE + def_bool n + help + Select when the board requires that the power button is always + enabled. + +config POWER_BUTTON_FORCE_DISABLE + def_bool n + help + Select when the board requires that the power button is always + disabled, e.g. when it has been hardwired to ground. + +config POWER_BUTTON_IS_OPTIONAL + bool + default y if POWER_BUTTON_DEFAULT_ENABLE || POWER_BUTTON_DEFAULT_DISABLE + default n if !(POWER_BUTTON_DEFAULT_ENABLE || POWER_BUTTON_DEFAULT_DISABLE) + help + Internal option that controls ENABLE_POWER_BUTTON visibility. + source src/Kconfig.deprecated_options