X-Git-Url: http://wien.tomnetworks.com/gitweb/?a=blobdiff_plain;f=src%2FKconfig;h=9153ca0675ebcb046ed819b1f9fcad7cc848b622;hb=0d5a6accc84530d44f35ba4f3a74b370a1f88f86;hp=1106d630ec6b1c87c99d4c341168beddbd8e441c;hpb=e696942cfc6d970d9a774815cc81bf1d771c857b;p=coreboot.git diff --git a/src/Kconfig b/src/Kconfig index 1106d630e..9153ca067 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -1,28 +1,20 @@ ## -## This file is part of the coreboot repair project. +## This file is part of the coreboot project. ## -## Redistribution and use in source and binary forms, with or without -## modification, are permitted provided that the following conditions -## are met: -## 1. Redistributions of source code must retain the above copyright -## notice, this list of conditions and the following disclaimer. -## 2. Redistributions in binary form must reproduce the above copyright -## notice, this list of conditions and the following disclaimer in the -## documentation and/or other materials provided with the distribution. -## 3. The name of the author may not be used to endorse or promote products -## derived from this software without specific prior written permission. +## Copyright (C) 2009-2010 coresystems GmbH ## -## THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND -## ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -## IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -## ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE -## FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -## DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS -## OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) -## HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -## LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY -## OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF -## SUCH DAMAGE. +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## mainmenu "Coreboot Configuration" @@ -47,6 +39,65 @@ config LOCALVERSION the coreboot version number, so that you can easily distinguish boot logs of different boards from each other. +config CBFS_PREFIX + string "CBFS prefix to use" + default "fallback" + help + Select the prefix to all files put into the image. It's "fallback" + by default, "normal" is a common alternative. + +choice + prompt "Compiler" + default COMPILER_GCC + help + This option allows you to select the compiler used for building + coreboot. + +config COMPILER_GCC + bool "GCC" +config COMPILER_LLVM_CLANG + bool "LLVM/clang" +endchoice + +config SCANBUILD_ENABLE + bool "Build with scan-build for static analysis" + default n + help + Changes the build process to scan-build is used. + Requires scan-build in path. + +config SCANBUILD_REPORT_LOCATION + string "Directory to put scan-build report in" + default "" + depends on SCANBUILD_ENABLE + help + Where the scan-build report should be stored + +config CCACHE + bool "ccache" + default n + help + Enables the use of ccache for faster builds. + Requires ccache in path. + +config SCONFIG_GENPARSER + bool "Generate SCONFIG parser using flex and bison" + default n + depends on EXPERT + help + Enable this option if you are working on the sconfig + device tree parser and made changes to sconfig.l and + sconfig.y. + Otherwise, say N. + +config USE_OPTION_TABLE + bool "Use CMOS for configuration values" + default n + depends on HAVE_OPTION_TABLE + help + Enable this option if coreboot shall read options from the "CMOS" + NVRAM instead of using hard coded values. + endmenu source src/mainboard/Kconfig @@ -67,6 +118,10 @@ source src/devices/Kconfig endmenu +menu "Generic Drivers" +source src/drivers/Kconfig +endmenu + config PCI_BUS_SEGN_BITS int default 0 @@ -83,26 +138,6 @@ config CPU_ADDR_BITS int default 36 -config XIP_ROM_BASE - hex - default 0xfffe0000 - -config XIP_ROM_SIZE - hex - default 0x20000 - -config LB_CKS_RANGE_START - int - default 49 - -config LB_CKS_RANGE_END - int - default 125 - -config LB_CKS_LOC - int - default 126 - config LOGICAL_CPUS bool default y @@ -115,26 +150,6 @@ config HEAP_SIZE hex default 0x4000 -config COREBOOT_V2 - bool - default y - -config COREBOOT_V4 - bool - default y - -config DEBUG - bool - default n - -config USE_PRINTK_IN_CAR - bool - default n - -config USE_OPTION_TABLE - bool - default n - config MAX_CPUS int default 1 @@ -147,10 +162,6 @@ config MMCONF_SUPPORT bool default n -config RAMTOP - hex - default 0x200000 - config ATI_RAGE_XL bool @@ -160,49 +171,42 @@ config HAVE_ACPI_RESUME bool default n -config ACPI_SSDTX_NUM - int - default 0 - -config HAVE_FALLBACK_BOOT - bool - default y - -config USE_FALLBACK_IMAGE - bool - default y - -config HAVE_FAILOVER_BOOT +config HAVE_ACPI_SLIC bool default n -config USE_FAILOVER_IMAGE - bool - default n +config ACPI_SSDTX_NUM + int + default 0 config HAVE_HARD_RESET bool + default y if BOARD_HAS_HARD_RESET default n + help + This variable specifies whether a given board has a hard_reset + function, no matter if it's provided by board code or chipset code. config HAVE_INIT_TIMER bool + default n if UDELAY_IO default y config HAVE_MAINBOARD_RESOURCES bool default n -config HAVE_MOVNTI +config USE_OPTION_TABLE bool default n config HAVE_OPTION_TABLE bool - default y + default n help This variable specifies whether a given board has a cmos.layout file containing NVRAM/CMOS bit definitions. - It defaults to 'y' but can be changed to 'n' in mainboard/*/Kconfig. + It defaults to 'n' but can be selected in mainboard/*/Kconfig. config PIRQ_ROUTE bool @@ -246,27 +250,6 @@ config GFXUMA # # endmenu -#TODO Remove this option or make it useful. -config HAVE_LOW_TABLES - bool - default y - help - This Option is unused in the code. Since two boards try to set it to - 'n', they may be broken. We either need to make the option useful or - get rid of it. The broken boards are: - asus/m2v-mx_se - supermicro/h8dme - -config HAVE_HIGH_TABLES - bool - default n - help - This variable specifies whether a given northbridge has high table - support. - It is set in northbridge/*/Kconfig. - Whether or not the high tables are actually written by coreboot is - configurable by the user via WRITE_HIGH_TABLES. - config HAVE_ACPI_TABLES bool help @@ -306,20 +289,15 @@ config GENERATE_PIRQ_TABLE bool default HAVE_PIRQ_TABLE -config WRITE_HIGH_TABLES - bool - default HAVE_HIGH_TABLES - menu "System tables" config WRITE_HIGH_TABLES bool "Write 'high' tables to avoid being overwritten in F segment" - depends on HAVE_HIGH_TABLES default y config MULTIBOOT bool "Generate Multiboot tables (for GRUB2)" - default n + default y config GENERATE_ACPI_TABLES depends on HAVE_ACPI_TABLES @@ -420,7 +398,7 @@ config FALLBACK_VGA_BIOS_FILE The path and filename of the file to use as VGA BIOS. config FALLBACK_VGA_BIOS_ID - string "VGA BIOS ID" + string "VGA device PCI IDs" depends on VGA_BIOS default "1106,3230" help @@ -433,6 +411,66 @@ config FALLBACK_VGA_BIOS_ID the "0x" prefix) and 3230 specifies the PCI device ID of the video card (also in hex, without "0x" prefix). +config INTEL_MBI + bool "Add an MBI image" + depends on NORTHBRIDGE_INTEL_I82830 + help + Select this option if you have an Intel MBI image that you would + like to add to your ROM. + + You will be able to specify the location and file name of the + image later. + +config FALLBACK_MBI_FILE + string "Intel MBI path and filename" + depends on INTEL_MBI + default "mbi.bin" + help + The path and filename of the file to use as VGA BIOS. + +endmenu + +menu "Bootsplash" + depends on PCI_OPTION_ROM_RUN_YABEL + +config BOOTSPLASH + prompt "Show graphical bootsplash" + bool + depends on PCI_OPTION_ROM_RUN_YABEL + help + This option shows a graphical bootsplash screen. The grapics are + loaded from the CBFS file bootsplash.jpg. + +config FALLBACK_BOOTSPLASH_FILE + string "Bootsplash path and filename" + depends on BOOTSPLASH + default "bootsplash.jpg" + help + The path and filename of the file to use as graphical bootsplash + screen. The file format has to be jpg. + +# TODO: Turn this into a "choice". +config FRAMEBUFFER_VESA_MODE + prompt "VESA framebuffer video mode" + hex + default 0x117 + depends on BOOTSPLASH + help + This option sets the resolution used for the coreboot framebuffer and + bootsplash screen. Set to 0x117 for 1024x768x16. A diligent soul will + some day make this a "choice". + +config COREBOOT_KEEP_FRAMEBUFFER + prompt "Keep VESA framebuffer" + bool + depends on BOOTSPLASH + help + This option keeps the framebuffer mode set after coreboot finishes + execution. If this option is enabled, coreboot will pass a + framebuffer entry in its coreboot table and the payload will need a + framebuffer driver. If this option is disabled, coreboot will switch + back to text mode before handing control to a payload. + endmenu menu "Debugging" @@ -445,6 +483,265 @@ config GDB_STUB If enabled, you will be able to set breakpoints for gdb debugging. See src/arch/i386/lib/c_start.S for details. +config HAVE_DEBUG_RAM_SETUP + def_bool n + +config DEBUG_RAM_SETUP + bool "Output verbose RAM init debug messages" + default n + depends on HAVE_DEBUG_RAM_SETUP + help + This option enables additional RAM init related debug messages. + It is recommended to enable this when debugging issues on your + board which might be RAM init related. + + Note: This option will increase the size of the coreboot image. + + If unsure, say N. + +config HAVE_DEBUG_CAR + def_bool n + +config DEBUG_CAR + def_bool n + depends on HAVE_DEBUG_CAR + +if DEFAULT_CONSOLE_LOGLEVEL_7 || DEFAULT_CONSOLE_LOGLEVEL_8 +# Only visible if debug level is DEBUG (7) or SPEW (8) as it does additional +# printk(BIOS_DEBUG, ...) calls. +config DEBUG_CAR + bool "Output verbose Cache-as-RAM debug messages" + default n + depends on HAVE_DEBUG_CAR + help + This option enables additional CAR related debug messages. +endif + +config DEBUG_PIRQ + bool "Check PIRQ table consistency" + default n + depends on GENERATE_PIRQ_TABLE + help + If unsure, say N. + +config HAVE_DEBUG_SMBUS + def_bool n + +config DEBUG_SMBUS + bool "Output verbose SMBus debug messages" + default n + depends on HAVE_DEBUG_SMBUS + help + This option enables additional SMBus (and SPD) debug messages. + + Note: This option will increase the size of the coreboot image. + + If unsure, say N. + +config DEBUG_SMI + bool "Output verbose SMI debug messages" + default n + depends on HAVE_SMI_HANDLER + help + This option enables additional SMI related debug messages. + + Note: This option will increase the size of the coreboot image. + + If unsure, say N. + +config DEBUG_SMM_RELOCATION + bool "Debug SMM relocation code" + default n + depends on HAVE_SMI_HANDLER + help + This option enables additional SMM handler relocation related + debug messages. + + Note: This option will increase the size of the coreboot image. + + If unsure, say N. + +config DEBUG_MALLOC + def_bool n + +# Only visible if debug level is DEBUG (7) or SPEW (8) as it does additional +# printk(BIOS_DEBUG, ...) calls. +if DEFAULT_CONSOLE_LOGLEVEL_7 || DEFAULT_CONSOLE_LOGLEVEL_8 +config DEBUG_MALLOC + bool "Output verbose malloc debug messages" + default n + help + This option enables additional malloc related debug messages. + + Note: This option will increase the size of the coreboot image. + + If unsure, say N. +endif + +config REALMODE_DEBUG + def_bool n + depends on PCI_OPTION_ROM_RUN_REALMODE + +if DEFAULT_CONSOLE_LOGLEVEL_7 || DEFAULT_CONSOLE_LOGLEVEL_8 +# Only visible if debug level is DEBUG (7) or SPEW (8) as it does additional +# printk(BIOS_DEBUG, ...) calls. +config REALMODE_DEBUG + bool "Enable debug messages for option ROM execution" + default n + depends on PCI_OPTION_ROM_RUN_REALMODE + help + This option enables additional x86emu related debug messages. + + Note: This option will increase the time to emulate a ROM. + + If unsure, say N. +endif + +config X86EMU_DEBUG + bool "Output verbose x86emu debug messages" + default n + depends on PCI_OPTION_ROM_RUN_YABEL + help + This option enables additional x86emu related debug messages. + + Note: This option will increase the size of the coreboot image. + + If unsure, say N. + +config X86EMU_DEBUG_JMP + bool "Trace JMP/RETF" + default n + depends on X86EMU_DEBUG + help + Print information about JMP and RETF opcodes from x86emu. + + Note: This option will increase the size of the coreboot image. + + If unsure, say N. + +config X86EMU_DEBUG_TRACE + bool "Trace all opcodes" + default n + depends on X86EMU_DEBUG + help + Print _all_ opcodes that are executed by x86emu. + + WARNING: This will produce a LOT of output and take a long time. + + Note: This option will increase the size of the coreboot image. + + If unsure, say N. + +config X86EMU_DEBUG_PNP + bool "Log Plug&Play accesses" + default n + depends on X86EMU_DEBUG + help + Print Plug And Play accesses made by option ROMs. + + Note: This option will increase the size of the coreboot image. + + If unsure, say N. + +config X86EMU_DEBUG_DISK + bool "Log Disk I/O" + default n + depends on X86EMU_DEBUG + help + Print Disk I/O related messages. + + Note: This option will increase the size of the coreboot image. + + If unsure, say N. + +config X86EMU_DEBUG_PMM + bool "Log PMM" + default n + depends on X86EMU_DEBUG + help + Print messages related to POST Memory Manager (PMM). + + Note: This option will increase the size of the coreboot image. + + If unsure, say N. + + +config X86EMU_DEBUG_VBE + bool "Debug VESA BIOS Extensions" + default n + depends on X86EMU_DEBUG + help + Print messages related to VESA BIOS Extension (VBE) functions. + + Note: This option will increase the size of the coreboot image. + + If unsure, say N. + +config X86EMU_DEBUG_INT10 + bool "Redirect INT10 output to console" + default n + depends on X86EMU_DEBUG + help + Let INT10 (i.e. character output) calls print messages to debug output. + + Note: This option will increase the size of the coreboot image. + + If unsure, say N. + +config X86EMU_DEBUG_INTERRUPTS + bool "Log intXX calls" + default n + depends on X86EMU_DEBUG + help + Print messages related to interrupt handling. + + Note: This option will increase the size of the coreboot image. + + If unsure, say N. + +config X86EMU_DEBUG_CHECK_VMEM_ACCESS + bool "Log special memory accesses" + default n + depends on X86EMU_DEBUG + help + Print messages related to accesses to certain areas of the virtual + memory (e.g. BDA (BIOS Data Area) or interrupt vectors) + + Note: This option will increase the size of the coreboot image. + + If unsure, say N. + +config X86EMU_DEBUG_MEM + bool "Log all memory accesses" + default n + depends on X86EMU_DEBUG + help + Print memory accesses made by option ROM. + Note: This also includes accesses to fetch instructions. + + Note: This option will increase the size of the coreboot image. + + If unsure, say N. + +config X86EMU_DEBUG_IO + bool "Log IO accesses" + default n + depends on X86EMU_DEBUG + help + Print I/O accesses made by option ROM. + + Note: This option will increase the size of the coreboot image. + + If unsure, say N. + +config LLSHELL + bool "Built-in low-level shell" + default n + help + If enabled, you will have a low level shell to examine your machine. + Put llshell() in your (romstage) code to start the shell. + See src/arch/i386/llshell/llshell.inc for details. + endmenu config LIFT_BSP_APIC_ID @@ -456,10 +753,59 @@ config AP_CODE_IN_CAR bool default n -config USE_INIT +config RAMINIT_SYSINFO bool default n config ENABLE_APIC_EXT_ID bool default n + +config WARNINGS_ARE_ERRORS + bool + default y + +config ID_SECTION_OFFSET + hex + default 0x10 + +# The four POWER_BUTTON_DEFAULT_ENABLE, POWER_BUTTON_DEFAULT_DISABLE, +# POWER_BUTTON_FORCE_ENABLE and POWER_BUTTON_FORCE_DISABLE options are +# mutually exclusive. One of these options must be selected in the +# mainboard Kconfig if the chipset supports enabling and disabling of +# the power button. Chipset code uses the ENABLE_POWER_BUTTON option set +# in mainboard/Kconfig to know if the button should be enabled or not. + +config POWER_BUTTON_DEFAULT_ENABLE + def_bool n + help + Select when the board has a power button which can optionally be + disabled by the user. + +config POWER_BUTTON_DEFAULT_DISABLE + def_bool n + help + Select when the board has a power button which can optionally be + enabled by the user, e.g. when the board ships with a jumper over + the power switch contacts. + +config POWER_BUTTON_FORCE_ENABLE + def_bool n + help + Select when the board requires that the power button is always + enabled. + +config POWER_BUTTON_FORCE_DISABLE + def_bool n + help + Select when the board requires that the power button is always + disabled, e.g. when it has been hardwired to ground. + +config POWER_BUTTON_IS_OPTIONAL + bool + default y if POWER_BUTTON_DEFAULT_ENABLE || POWER_BUTTON_DEFAULT_DISABLE + default n if !(POWER_BUTTON_DEFAULT_ENABLE || POWER_BUTTON_DEFAULT_DISABLE) + help + Internal option that controls ENABLE_POWER_BUTTON visibility. + +source src/Kconfig.deprecated_options