X-Git-Url: http://wien.tomnetworks.com/gitweb/?a=blobdiff_plain;f=src%2FKconfig;h=77546b05909ca35104705bc1c4e97aff7827ded6;hb=cef3b896c1593de5a41b57bff4d4600d0c90e06e;hp=75f50aa048af7b9badecc8f403ebef213c2cfa25;hpb=55cf7bcbeb605648ccfa2fdab102506f87388c07;p=coreboot.git diff --git a/src/Kconfig b/src/Kconfig index 75f50aa04..77546b059 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -46,88 +46,77 @@ config CBFS_PREFIX Select the prefix to all files put into the image. It's "fallback" by default, "normal" is a common alternative. -endmenu +choice + prompt "Compiler" + default COMPILER_GCC + help + This option allows you to select the compiler used for building + coreboot. -source src/mainboard/Kconfig -source src/arch/i386/Kconfig +config COMPILER_GCC + bool "GCC" +config COMPILER_LLVM_CLANG + bool "LLVM/clang" +endchoice -menu "Chipset" +config SCANBUILD_ENABLE + bool "Build with scan-build for static analysis" + default n + help + Changes the build process to scan-build is used. + Requires scan-build in path. -comment "CPU" -source src/cpu/Kconfig -comment "Northbridge" +config SCANBUILD_REPORT_LOCATION + string "Directory to put scan-build report in" + default "" + depends on SCANBUILD_ENABLE + help + Where the scan-build report should be stored -menu "HyperTransport Setup" - depends on (NORTHBRIDGE_AMD_AMDK8 || NORTHBRIDGE_AMD_AMDFAM10) && EXPERT +config CCACHE + bool "ccache" + default n + help + Enables the use of ccache for faster builds. + Requires ccache in path. -choice - prompt "HyperTransport Frequency" - default LIMIT_HT_SPEED_AUTO - help - This option sets the maximum permissible HyperTransport link frequency. - Use of this option will only limit the autodetected HT frequency; it will not (and cannot) increase the frequency beyond the autodetected limits. - This is primarily used to work around poorly designed or laid out HT traces on certain motherboards. - -config LIMIT_HT_SPEED_200 - bool "Limit HT frequency to 200MHz" -config LIMIT_HT_SPEED_400 - bool "Limit HT frequency to 400MHz" -config LIMIT_HT_SPEED_600 - bool "Limit HT frequency to 600MHz" -config LIMIT_HT_SPEED_800 - bool "Limit HT frequency to 800MHz" -config LIMIT_HT_SPEED_1000 - bool "Limit HT frequency to 1.0GHz" -config LIMIT_HT_SPEED_1200 - bool "Limit HT frequency to 1.2GHz" -config LIMIT_HT_SPEED_1400 - bool "Limit HT frequency to 1.4GHz" -config LIMIT_HT_SPEED_1600 - bool "Limit HT frequency to 1.6GHz" -config LIMIT_HT_SPEED_1800 - bool "Limit HT frequency to 1.6GHz" -config LIMIT_HT_SPEED_2000 - bool "Limit HT frequency to 2.0GHz" -config LIMIT_HT_SPEED_2200 - bool "Limit HT frequency to 2.2GHz" -config LIMIT_HT_SPEED_2400 - bool "Limit HT frequency to 2.4GHz" -config LIMIT_HT_SPEED_2600 - bool "Limit HT frequency to 2.6GHz" -config LIMIT_HT_SPEED_AUTO - bool "Autodetect HT frequency" -endchoice +config SCONFIG_GENPARSER + bool "Generate SCONFIG parser using flex and bison" + default n + depends on EXPERT + help + Enable this option if you are working on the sconfig + device tree parser and made changes to sconfig.l and + sconfig.y. + Otherwise, say N. -choice - prompt "HyperTransport Downlink Width" - default LIMIT_HT_DOWN_WIDTH_16 +config USE_OPTION_TABLE + bool "Use CMOS for configuration values" + default n + depends on HAVE_OPTION_TABLE help - This option sets the maximum permissible HyperTransport link width. - Use of this option will only limit the autodetected HT width; it will not (and cannot) increase the width beyond the autodetected limits. - This is primarily used to work around poorly designed or laid out HT traces on certain motherboards. + Enable this option if coreboot shall read options from the "CMOS" + NVRAM instead of using hard coded values. -config LIMIT_HT_DOWN_WIDTH_8 - bool "8 bits" -config LIMIT_HT_DOWN_WIDTH_16 - bool "16 bits" -endchoice +endmenu -choice - prompt "HyperTransport Uplink Width" - default LIMIT_HT_UP_WIDTH_16 - help - This option sets the maximum permissible HyperTransport link width. - Use of this option will only limit the autodetected HT width; it will not (and cannot) increase the width beyond the autodetected limits. - This is primarily used to work around poorly designed or laid out HT traces on certain motherboards. +source src/mainboard/Kconfig -config LIMIT_HT_UP_WIDTH_8 - bool "8 bits" -config LIMIT_HT_UP_WIDTH_16 - bool "16 bits" -endchoice +# This option is used to set the architecture of a mainboard to X86. +# It is usually set in mainboard/*/Kconfig. +config ARCH_X86 + bool + default n -endmenu +if ARCH_X86 +source src/arch/x86/Kconfig +endif +menu "Chipset" + +comment "CPU" +source src/cpu/Kconfig +comment "Northbridge" source src/northbridge/Kconfig comment "Southbridge" source src/southbridge/Kconfig @@ -138,6 +127,10 @@ source src/devices/Kconfig endmenu +menu "Generic Drivers" +source src/drivers/Kconfig +endmenu + config PCI_BUS_SEGN_BITS int default 0 @@ -149,35 +142,6 @@ config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID hex default 0x0 - -config CPU_ADDR_BITS - int - default 36 - -config XIP_ROM_BASE - hex - default 0xfffe0000 - -config XIP_ROM_SIZE - hex - default 0x20000 - -config LB_CKS_RANGE_START - int - default 49 - -config LB_CKS_RANGE_END - int - default 125 - -config LB_CKS_LOC - int - default 126 - -config LOGICAL_CPUS - bool - default y - config PCI_ROM_RUN bool default n @@ -186,18 +150,6 @@ config HEAP_SIZE hex default 0x4000 -config DEBUG - bool - default n - -config USE_PRINTK_IN_CAR - bool - default n - -config USE_OPTION_TABLE - bool - default n - config MAX_CPUS int default 1 @@ -210,10 +162,6 @@ config MMCONF_SUPPORT bool default n -config RAMTOP - hex - default 0x200000 - config ATI_RAGE_XL bool @@ -223,25 +171,13 @@ config HAVE_ACPI_RESUME bool default n -config ACPI_SSDTX_NUM - int - default 0 - -config HAVE_FALLBACK_BOOT - bool - default y - -config USE_FALLBACK_IMAGE - bool - default y - -config HAVE_FAILOVER_BOOT +config HAVE_ACPI_SLIC bool default n -config USE_FAILOVER_IMAGE - bool - default n +config ACPI_SSDTX_NUM + int + default 0 config HAVE_HARD_RESET bool @@ -251,28 +187,6 @@ config HAVE_HARD_RESET This variable specifies whether a given board has a hard_reset function, no matter if it's provided by board code or chipset code. -config BOARD_HAS_HARD_RESET - bool - default n - help - This variable specifies whether a given board has a reset.c - file containing a hard_reset() function. - -config BOARD_HAS_FADT - bool - default n - help - This variable specifies whether a given board has a board-local - FADT in fadt.c. Long-term, those should be moved to appropriate - chipset components (eg. southbridge) - -config HAVE_BUS_CONFIG - bool - default n - help - This variable specifies whether a given board has a get_bus_conf.c - file containing bus configuration data. - config HAVE_INIT_TIMER bool default n if UDELAY_IO @@ -282,13 +196,17 @@ config HAVE_MAINBOARD_RESOURCES bool default n +config USE_OPTION_TABLE + bool + default n + config HAVE_OPTION_TABLE bool - default y + default n help This variable specifies whether a given board has a cmos.layout file containing NVRAM/CMOS bit definitions. - It defaults to 'y' but can be changed to 'n' in mainboard/*/Kconfig. + It defaults to 'n' but can be selected in mainboard/*/Kconfig. config PIRQ_ROUTE bool @@ -332,27 +250,6 @@ config GFXUMA # # endmenu -#TODO Remove this option or make it useful. -config HAVE_LOW_TABLES - bool - default y - help - This Option is unused in the code. Since two boards try to set it to - 'n', they may be broken. We either need to make the option useful or - get rid of it. The broken boards are: - asus/m2v-mx_se - supermicro/h8dme - -config HAVE_HIGH_TABLES - bool - default y - help - This variable specifies whether a given northbridge has high table - support. - It is set in northbridge/*/Kconfig. - Whether or not the high tables are actually written by coreboot is - configurable by the user via WRITE_HIGH_TABLES. - config HAVE_ACPI_TABLES bool help @@ -392,15 +289,10 @@ config GENERATE_PIRQ_TABLE bool default HAVE_PIRQ_TABLE -config WRITE_HIGH_TABLES - bool - default HAVE_HIGH_TABLES - menu "System tables" config WRITE_HIGH_TABLES bool "Write 'high' tables to avoid being overwritten in F segment" - depends on HAVE_HIGH_TABLES default y config MULTIBOOT @@ -441,7 +333,8 @@ menu "Payload" choice prompt "Add a payload" - default PAYLOAD_NONE + default PAYLOAD_NONE if !ARCH_X86 + default PAYLOAD_SEABIOS if ARCH_X86 config PAYLOAD_NONE bool "None" @@ -463,20 +356,49 @@ config PAYLOAD_ELF You will be able to specify the location and file name of the payload image later. +config PAYLOAD_SEABIOS + bool "SeaBIOS" + depends on ARCH_X86 + help + Select this option if you want to build a coreboot image + with a SeaBIOS payload. If you don't know what this is + about, just leave it enabled. + + See http://coreboot.org/Payloads for more information. + endchoice -config FALLBACK_PAYLOAD_FILE +choice + prompt "SeaBIOS version" + default SEABIOS_STABLE + depends on PAYLOAD_SEABIOS + +config SEABIOS_STABLE + bool "stable" + help + Stable SeaBIOS version +config SEABIOS_MASTER + bool "master" + help + Newest SeaBIOS version +endchoice + +config PAYLOAD_FILE string "Payload path and filename" depends on PAYLOAD_ELF default "payload.elf" help The path and filename of the ELF executable file to use as payload. +config PAYLOAD_FILE + depends on PAYLOAD_SEABIOS + default "payloads/external/SeaBIOS/seabios/out/bios.bin.elf" + # TODO: Defined if no payload? Breaks build? config COMPRESSED_PAYLOAD_LZMA bool "Use LZMA compression for payloads" default y - depends on PAYLOAD_ELF + depends on PAYLOAD_ELF || PAYLOAD_SEABIOS help In order to reduce the size payloads take up in the ROM chip coreboot can compress them using the LZMA algorithm. @@ -498,14 +420,14 @@ config VGA_BIOS You will be able to specify the location and file name of the image later. -config FALLBACK_VGA_BIOS_FILE +config VGA_BIOS_FILE string "VGA BIOS path and filename" depends on VGA_BIOS default "vgabios.bin" help The path and filename of the file to use as VGA BIOS. -config FALLBACK_VGA_BIOS_ID +config VGA_BIOS_ID string "VGA device PCI IDs" depends on VGA_BIOS default "1106,3230" @@ -529,7 +451,7 @@ config INTEL_MBI You will be able to specify the location and file name of the image later. -config FALLBACK_MBI_FILE +config MBI_FILE string "Intel MBI path and filename" depends on INTEL_MBI default "mbi.bin" @@ -549,13 +471,13 @@ config BOOTSPLASH This option shows a graphical bootsplash screen. The grapics are loaded from the CBFS file bootsplash.jpg. -config FALLBACK_BOOTSPLASH_FILE +config BOOTSPLASH_FILE string "Bootsplash path and filename" depends on BOOTSPLASH default "bootsplash.jpg" help - The path and filename of the file to use as graphical bootsplash - screen. The file format has to be jpg. + The path and filename of the file to use as graphical bootsplash + screen. The file format has to be jpg. # TODO: Turn this into a "choice". config FRAMEBUFFER_VESA_MODE @@ -589,7 +511,266 @@ config GDB_STUB default y help If enabled, you will be able to set breakpoints for gdb debugging. - See src/arch/i386/lib/c_start.S for details. + See src/arch/x86/lib/c_start.S for details. + +config HAVE_DEBUG_RAM_SETUP + def_bool n + +config DEBUG_RAM_SETUP + bool "Output verbose RAM init debug messages" + default n + depends on HAVE_DEBUG_RAM_SETUP + help + This option enables additional RAM init related debug messages. + It is recommended to enable this when debugging issues on your + board which might be RAM init related. + + Note: This option will increase the size of the coreboot image. + + If unsure, say N. + +config HAVE_DEBUG_CAR + def_bool n + +config DEBUG_CAR + def_bool n + depends on HAVE_DEBUG_CAR + +if DEFAULT_CONSOLE_LOGLEVEL_7 || DEFAULT_CONSOLE_LOGLEVEL_8 +# Only visible if debug level is DEBUG (7) or SPEW (8) as it does additional +# printk(BIOS_DEBUG, ...) calls. +config DEBUG_CAR + bool "Output verbose Cache-as-RAM debug messages" + default n + depends on HAVE_DEBUG_CAR + help + This option enables additional CAR related debug messages. +endif + +config DEBUG_PIRQ + bool "Check PIRQ table consistency" + default n + depends on GENERATE_PIRQ_TABLE + help + If unsure, say N. + +config HAVE_DEBUG_SMBUS + def_bool n + +config DEBUG_SMBUS + bool "Output verbose SMBus debug messages" + default n + depends on HAVE_DEBUG_SMBUS + help + This option enables additional SMBus (and SPD) debug messages. + + Note: This option will increase the size of the coreboot image. + + If unsure, say N. + +config DEBUG_SMI + bool "Output verbose SMI debug messages" + default n + depends on HAVE_SMI_HANDLER + help + This option enables additional SMI related debug messages. + + Note: This option will increase the size of the coreboot image. + + If unsure, say N. + +config DEBUG_SMM_RELOCATION + bool "Debug SMM relocation code" + default n + depends on HAVE_SMI_HANDLER + help + This option enables additional SMM handler relocation related + debug messages. + + Note: This option will increase the size of the coreboot image. + + If unsure, say N. + +config DEBUG_MALLOC + def_bool n + +# Only visible if debug level is DEBUG (7) or SPEW (8) as it does additional +# printk(BIOS_DEBUG, ...) calls. +if DEFAULT_CONSOLE_LOGLEVEL_7 || DEFAULT_CONSOLE_LOGLEVEL_8 +config DEBUG_MALLOC + bool "Output verbose malloc debug messages" + default n + help + This option enables additional malloc related debug messages. + + Note: This option will increase the size of the coreboot image. + + If unsure, say N. +endif + +config REALMODE_DEBUG + def_bool n + depends on PCI_OPTION_ROM_RUN_REALMODE + +if DEFAULT_CONSOLE_LOGLEVEL_7 || DEFAULT_CONSOLE_LOGLEVEL_8 +# Only visible if debug level is DEBUG (7) or SPEW (8) as it does additional +# printk(BIOS_DEBUG, ...) calls. +config REALMODE_DEBUG + bool "Enable debug messages for option ROM execution" + default n + depends on PCI_OPTION_ROM_RUN_REALMODE + help + This option enables additional x86emu related debug messages. + + Note: This option will increase the time to emulate a ROM. + + If unsure, say N. +endif + +config X86EMU_DEBUG + bool "Output verbose x86emu debug messages" + default n + depends on PCI_OPTION_ROM_RUN_YABEL + help + This option enables additional x86emu related debug messages. + + Note: This option will increase the size of the coreboot image. + + If unsure, say N. + +config X86EMU_DEBUG_JMP + bool "Trace JMP/RETF" + default n + depends on X86EMU_DEBUG + help + Print information about JMP and RETF opcodes from x86emu. + + Note: This option will increase the size of the coreboot image. + + If unsure, say N. + +config X86EMU_DEBUG_TRACE + bool "Trace all opcodes" + default n + depends on X86EMU_DEBUG + help + Print _all_ opcodes that are executed by x86emu. + + WARNING: This will produce a LOT of output and take a long time. + + Note: This option will increase the size of the coreboot image. + + If unsure, say N. + +config X86EMU_DEBUG_PNP + bool "Log Plug&Play accesses" + default n + depends on X86EMU_DEBUG + help + Print Plug And Play accesses made by option ROMs. + + Note: This option will increase the size of the coreboot image. + + If unsure, say N. + +config X86EMU_DEBUG_DISK + bool "Log Disk I/O" + default n + depends on X86EMU_DEBUG + help + Print Disk I/O related messages. + + Note: This option will increase the size of the coreboot image. + + If unsure, say N. + +config X86EMU_DEBUG_PMM + bool "Log PMM" + default n + depends on X86EMU_DEBUG + help + Print messages related to POST Memory Manager (PMM). + + Note: This option will increase the size of the coreboot image. + + If unsure, say N. + + +config X86EMU_DEBUG_VBE + bool "Debug VESA BIOS Extensions" + default n + depends on X86EMU_DEBUG + help + Print messages related to VESA BIOS Extension (VBE) functions. + + Note: This option will increase the size of the coreboot image. + + If unsure, say N. + +config X86EMU_DEBUG_INT10 + bool "Redirect INT10 output to console" + default n + depends on X86EMU_DEBUG + help + Let INT10 (i.e. character output) calls print messages to debug output. + + Note: This option will increase the size of the coreboot image. + + If unsure, say N. + +config X86EMU_DEBUG_INTERRUPTS + bool "Log intXX calls" + default n + depends on X86EMU_DEBUG + help + Print messages related to interrupt handling. + + Note: This option will increase the size of the coreboot image. + + If unsure, say N. + +config X86EMU_DEBUG_CHECK_VMEM_ACCESS + bool "Log special memory accesses" + default n + depends on X86EMU_DEBUG + help + Print messages related to accesses to certain areas of the virtual + memory (e.g. BDA (BIOS Data Area) or interrupt vectors) + + Note: This option will increase the size of the coreboot image. + + If unsure, say N. + +config X86EMU_DEBUG_MEM + bool "Log all memory accesses" + default n + depends on X86EMU_DEBUG + help + Print memory accesses made by option ROM. + Note: This also includes accesses to fetch instructions. + + Note: This option will increase the size of the coreboot image. + + If unsure, say N. + +config X86EMU_DEBUG_IO + bool "Log IO accesses" + default n + depends on X86EMU_DEBUG + help + Print I/O accesses made by option ROM. + + Note: This option will increase the size of the coreboot image. + + If unsure, say N. + +config LLSHELL + bool "Built-in low-level shell" + default n + help + If enabled, you will have a low level shell to examine your machine. + Put llshell() in your (romstage) code to start the shell. + See src/arch/x86/llshell/llshell.inc for details. endmenu @@ -602,7 +783,7 @@ config AP_CODE_IN_CAR bool default n -config USE_INIT +config RAMINIT_SYSINFO bool default n @@ -612,8 +793,49 @@ config ENABLE_APIC_EXT_ID config WARNINGS_ARE_ERRORS bool - default n + default y config ID_SECTION_OFFSET hex default 0x10 + +# The four POWER_BUTTON_DEFAULT_ENABLE, POWER_BUTTON_DEFAULT_DISABLE, +# POWER_BUTTON_FORCE_ENABLE and POWER_BUTTON_FORCE_DISABLE options are +# mutually exclusive. One of these options must be selected in the +# mainboard Kconfig if the chipset supports enabling and disabling of +# the power button. Chipset code uses the ENABLE_POWER_BUTTON option set +# in mainboard/Kconfig to know if the button should be enabled or not. + +config POWER_BUTTON_DEFAULT_ENABLE + def_bool n + help + Select when the board has a power button which can optionally be + disabled by the user. + +config POWER_BUTTON_DEFAULT_DISABLE + def_bool n + help + Select when the board has a power button which can optionally be + enabled by the user, e.g. when the board ships with a jumper over + the power switch contacts. + +config POWER_BUTTON_FORCE_ENABLE + def_bool n + help + Select when the board requires that the power button is always + enabled. + +config POWER_BUTTON_FORCE_DISABLE + def_bool n + help + Select when the board requires that the power button is always + disabled, e.g. when it has been hardwired to ground. + +config POWER_BUTTON_IS_OPTIONAL + bool + default y if POWER_BUTTON_DEFAULT_ENABLE || POWER_BUTTON_DEFAULT_DISABLE + default n if !(POWER_BUTTON_DEFAULT_ENABLE || POWER_BUTTON_DEFAULT_DISABLE) + help + Internal option that controls ENABLE_POWER_BUTTON visibility. + +source src/Kconfig.deprecated_options