X-Git-Url: http://wien.tomnetworks.com/gitweb/?a=blobdiff_plain;f=progs%2Fdt_inc.s;h=d680464490e414bc3f52f77425306556bd034287;hb=a3f2e6bb36ab614639c74e6fae9aca02b3a48578;hp=adedc502b23d832f555c7b090a5354894c8adee9;hpb=7bd87d5c82d7b1f7e86a15b0e6f1940020c87330;p=calu.git diff --git a/progs/dt_inc.s b/progs/dt_inc.s index adedc50..d680464 100644 --- a/progs/dt_inc.s +++ b/progs/dt_inc.s @@ -1,7 +1,6 @@ .data -; TODO -.org 0x300 +.org 0xA00 int2hex: ;3210 .fill 0x33323130 @@ -12,8 +11,7 @@ int2hex: ;fedc .fill 0x66656463 .text -; TODO -.org 0x300 +.org 0x400 .define UART_BASE, 0x2000 .define UART_STATUS, 0x0 .define UART_RECV, 0xc @@ -22,40 +20,45 @@ int2hex: .define UART_TRANS_EMPTY, 0x1 .define UART_RECV_NEW, 0x2 + .define PBASE, 0x2030 + .define PADDR, 0x4 + .define PDATA, 0x8 + + .define SSEG_BASE, 0x2010 + + .define INT_BASE, 0x2020 + .define INT_CONF, 0x04 + .define INT_GLOBAL_BIT, 0x01 + .define INT_UART_REC_BIT, 0x02 + + .define TIMER_BASE, 0x2040 + .define TIMER_STCFG, 0x0 + .define TIMER_VAL, 0x4 + u_recv_byte: -#ifndef DTSIM ldw r3, UART_STATUS(r10) andx r3, UART_RECV_NEW brzs+ u_recv_byte; branch if zero xor r0, r0, r0 ldw r0, UART_RECV(r10) -#else - ldis r0, 0x41 ; 'A' -#endif ret u_send_byte: -#ifndef DTSIM ldw r9, UART_STATUS(r10) andx r9, UART_TRANS_EMPTY brnz+ u_send_byte ; branch if not zero stb r1, UART_TRANS(r10) -#endif ret u_send_uint: -#ifndef DTSIM addi r8, r1, 0 ;usb_sendbuffersafe ("0x", 2); - xor r1, r1, r1 ldi r1, 0x30 call u_send_byte - xor r1, r1, r1 ldi r1, 0x78 call u_send_byte ;j = 0 xor r7, r7, r7 - xor r6, r6, r6 ldi r6, int2hex@lo ldih r6, int2hex@hi u_send_uint_loop: @@ -72,12 +75,8 @@ u_send_uint_loop: lls r8, r8, 4 addi r7, r7, 1 br u_send_uint_loop -#else - ret -#endif u_send_string: -#ifndef DTSIM ; r1 = addr ; r2 = len addi r3, r1, 0 @@ -89,24 +88,46 @@ u_send_string_int: addis r2, r2, 0-1 addi r3, r3, 1 br u_send_string_int -#else - ret -#endif u_send_newline: -#ifndef DTSIM - xor r1, r1, r1 ldi r1, 0x0a call u_send_byte ldi r1, 0x0d call u_send_byte -#endif ret u_init: -#ifndef DTSIM - xor r10, r10, r10 ldi r10, UART_BASE@lo ldih r10, UART_BASE@hi -#endif ret + +sseg_displ: + ldi r2, SSEG_BASE + stw r1, 0(r2) + ret + +t_init: + ldis r11, TIMER_BASE@lo + ldih r11, TIMER_BASE@hi + ret + +t_start: + ldis r1, 0x1 + stw r1, TIMER_STCFG(r11) + ret + +t_stop: + ldis r1, 0x0 + stw r1, TIMER_STCFG(r11) + ret + +t_valget: + ldw r0, TIMER_VAL(r11) + ret + +t_valset: + stw r1, TIMER_VAL(r11) + ret + +;for deepjit: start for programarea +prog_start: