X-Git-Url: http://wien.tomnetworks.com/gitweb/?a=blobdiff_plain;f=mono%2Fmini%2Fcpu-sparc.md;h=183f927fe0fd9cf2fe2da7ca92ba537b4f60c137;hb=c2d511e567dd2d535056dc79b745f88b4fb64afa;hp=f07e12a934f7e7bfbdae8fe3f137ef530e3551fc;hpb=5db2c4a3024a423ddb342e2dcfcd21ce26260fcb;p=mono.git

diff --git a/mono/mini/cpu-sparc.md b/mono/mini/cpu-sparc.md
index f07e12a934f..183f927fe0f 100644
--- a/mono/mini/cpu-sparc.md
+++ b/mono/mini/cpu-sparc.md
@@ -15,7 +15,9 @@
 #	i  integer register
 #	b  base register (used in address references)
 #	f  floating point register
-#   l  register pair
+#   L  register pair (same as 'i' on v9)
+#   l  %o0:%o1 register pair (same as 'i' on v9)
+#   o  %o0
 #
 # len:number         describe the maximun length in bytes of the instruction
 # number is a positive integer
@@ -45,503 +47,272 @@
 #
 # See the code in mini-sparc32.c for more details on how the specifiers are used.
 #
-nop: len:4
-break: len:4
-ldarg.0:
-ldarg.1:
-ldarg.2:
-ldarg.3:
-ldloc.0:
-ldloc.1:
-ldloc.2:
-ldloc.3:
-stloc.0:
-stloc.1:
-stloc.2:
-stloc.3:
-ldarg.s:
-ldarga.s:
-starg.s:
-ldloc.s:
-ldloca.s:
-stloc.s:
-ldnull:
-ldc.i4.m1:
-ldc.i4.0:
-ldc.i4.1:
-ldc.i4.2:
-ldc.i4.3:
-ldc.i4.4:
-ldc.i4.5:
-ldc.i4.6:
-ldc.i4.7:
-ldc.i4.8:
-ldc.i4.s:
-ldc.i4:
-ldc.i8:
-ldc.r4:
-ldc.r8:
-dup:
-pop:
-jmp:
-call: dest:i clob:c len:12
-calli:
-ret:
-br.s:
-brfalse.s:
-brtrue.s:
-beq.s:
-bge.s:
-bgt.s:
-ble.s:
-blt.s:
-bne.un.s:
-bge.un.s:
-bgt.un.s:
-ble.un.s:
-blt.un.s:
+label: len:0
+break: len:64
+jmp: len:64
 br: len:8
-brfalse:
-brtrue:
-beq: len:8
-bge: len:8
-bgt: len:8
-ble: len:8
-blt: len:8
-bne.un: len:16
-bge.un: len:16
-bgt.un: len:16
-ble.un: len:16
-blt.un: len:16
-switch:
-ldind.i1: dest:i len:4
-ldind.u1: dest:i len:4
-ldind.i2: dest:i len:4
-ldind.u2: dest:i len:4
-ldind.i4: dest:i len:4
-ldind.u4: dest:i len:4
-ldind.i8:
-ldind.i: dest:i len:4
-ldind.r4:
-ldind.r8:
-ldind.ref: dest:i len:4
-stind.ref: src1:b src2:i
-stind.i1: src1:b src2:i
-stind.i2: src1:b src2:i
-stind.i4: src1:b src2:i
-stind.i8:
-stind.r4: src1:b src2:f
-stind.r8: src1:b src2:f
-add: dest:i src1:i src2:i len:4
-sub: dest:i src1:i src2:i len:4
-mul: dest:i src1:i src2:i len:4
-div: dest:i src1:i src2:i len:12
-div.un: dest:i src1:i src2:i len:8
-rem: dest:d src1:i src2:i len:20
-rem.un: dest:d src1:i src2:i len:16
-and: dest:i src1:i src2:i len:4
-or: dest:i src1:i src2:i len:4
-xor: dest:i src1:i src2:i len:4
-shl: dest:i src1:i src2:i len:4
-shr: dest:i src1:i src2:i len:4
-shr.un: dest:i src1:i src2:i len:4
-neg: dest:i src1:i len:4
-not: dest:i src1:i len:4
-conv.i1: dest:i src1:i len:8
-conv.i2: dest:i src1:i len:8
-conv.i4: dest:i src1:i len:4
-conv.i8:
-conv.r4: dest:f src1:i len:16
-conv.r8: dest:f src1:i len:4
-conv.u4: dest:i src1:i len:
-conv.u8:
-callvirt:
-cpobj:
-ldobj:
-ldstr:
-newobj:
-castclass:
-isinst:
-conv.r.un:
-unbox:
-throw: src1:i len:8
-ldfld:
-ldflda:
-stfld:
-ldsfld:
-ldsflda:
-stsfld:
-stobj:
-conv.ovf.i1.un:
-conv.ovf.i2.un:
-conv.ovf.i4.un:
-conv.ovf.i8.un:
-conv.ovf.u1.un:
-conv.ovf.u2.un:
-conv.ovf.u4.un:
-conv.ovf.u8.un:
-conv.ovf.i.un:
-conv.ovf.u.un:
-box:
-newarr:
-ldlen:
-ldelema:
-ldelem.i1:
-ldelem.u1:
-ldelem.i2:
-ldelem.u2:
-ldelem.i4:
-ldelem.u4:
-ldelem.i8:
-ldelem.i:
-ldelem.r4:
-ldelem.r8:
-ldelem.ref:
-stelem.i:
-stelem.i1:
-stelem.i2:
-stelem.i4:
-stelem.i8:
-stelem.r4:
-stelem.r8:
-stelem.ref:
-conv.ovf.i1:
-conv.ovf.u1:
-conv.ovf.i2:
-conv.ovf.u2:
-conv.ovf.i4:
-conv.ovf.u4:
-conv.ovf.i8:
-conv.ovf.u8:
-refanyval:
-ckfinite: dest:f src1:f len:28
-mkrefany:
-ldtoken:
-conv.u2: dest:i src1:i len:8
-conv.u1: dest:i src1:i len:4
-conv.i: dest:i src1:i len:4
-conv.ovf.i:
-conv.ovf.u:
-add.ovf:
-add.ovf.un:
-mul.ovf: dest:i src1:i src2:i len:12
-mul.ovf.un: dest:i src1:i src2:i len:12
-sub.ovf:
-sub.ovf.un:
-# FIXME: May need some work
-endfinally: len:4
-leave:
-leave.s:
-stind.i:
-conv.u: dest:i src1:i len:4
-prefix7:
-prefix6:
-prefix5:
-prefix4:
-prefix3:
-prefix2:
-prefix1:
-prefixref:
-arglist:
-ceq: dest:i len:12
-cgt: dest:i len:12
-cgt.un: dest:i len:12
-clt: dest:i len:12
-clt.un: dest:i len:12
-ldftn:
-ldvirtftn:
-ldarg:
-ldarga:
-starg:
-ldloc:
-ldloca:
-stloc:
-# FIXME: WTF?!?
-localloc: dest:i src1:i len:30
-endfilter:
-unaligned.:
-volatile.:
-tail.:
-initobj:
-cpblk:
-initblk:
-rethrow:
-sizeof:
-refanytype:
-illegal:
-endmac:
-mono_func1:
-mono_proc2:
-mono_proc3:
-mono_free:
-mono_objaddr:
-mono_ldptr:
-mono_vtaddr:
-mono_newobj:
-mono_retobj:
-load:
-ldaddr:
-store:
-phi:
-rename:
+
+throw: src1:i len:64
+rethrow: src1:i len:64
+start_handler: len:64
+endfinally: len:64
+endfilter: src1:i len:64
+
+ckfinite: dest:f src1:f len:40
+ceq: dest:i len:64
+cgt: dest:i len:64
+cgt.un: dest:i len:64
+clt: dest:i len:64
+clt.un: dest:i len:64
+localloc: dest:i src1:i len:64
+localloc_imm: dest:i len:64
 compare: src1:i src2:i len:4
-compare_imm: src1:i len:12
-fcompare: src1:f src2:f len:12
-lcompare:
-local:
-arg:
-# FIXME: Mono-specifc opcodes (OP_)  Need to clean these up
-outarg: src1:i len:1
-outarg_imm: len:5
-retarg:
-setret: dest:a src1:i len:4
-setlret: dest:l src1:i src2:i len:8
-setreg: dest:i src1:i len:4 clob:r
-setregimm: dest:i len:8 clob:r
-setfreg: dest:f src1:f len:4 clob:r
+icompare: src1:i src2:i len:4
+compare_imm: src1:i len:64
+icompare_imm: src1:i len:64
+fcompare: src1:f src2:f len:64
+lcompare: src1:i src2:i len:4
+setfret: dest:f src1:f len:8
 checkthis: src1:b len:4
-voidcall: len:8 clob:c
-voidcall_reg: src1:i len:8 clob:c
-voidcall_membase: src1:b len:12 clob:c
-fcall: dest:f len:16 clob:c
-fcall_reg: dest:f src1:i len:16 clob:c
-fcall_membase: dest:f src1:b len:20 clob:c
-lcall: dest:l len:16 clob:c
-lcall_reg: dest:l src1:i len:16 clob:c
-lcall_membase: dest:l src1:b len:20 clob:c
-vcall: len:8 clob:c
-vcall_reg: src1:i len:8 clob:c
-vcall_membase: src1:b len:16 clob:c
-call_reg: dest:i src1:i len:12 clob:c
-call_membase: dest:i src1:b len:16 clob:c
-trap:
-iconst: dest:i len:8
-i8const:
-r4const: dest:f len:16
-r8const: dest:f len:12
-regvar:
-reg:
-regoffset:
-label:
-store_membase_imm: dest:b len:12
-store_membase_reg: dest:b src1:i len:8
-storei1_membase_imm: dest:b len:12
-storei1_membase_reg: dest:b src1:i len:8
-storei2_membase_imm: dest:b len:12
-storei2_membase_reg: dest:b src1:i len:8
-storei4_membase_imm: dest:b len:12
-storei4_membase_reg: dest:b src1:i len:8
-storei8_membase_imm: dest:b 
-storei8_membase_reg: dest:b src1:i len:4
-storer4_membase_reg: dest:b src1:f len:8
-storer8_membase_reg: dest:b src1:f len:12
-load_membase: dest:i src1:b len:12
-loadi1_membase: dest:i src1:b len:12
-loadu1_membase: dest:i src1:b len:12
-loadi2_membase: dest:i src1:b len:12
-loadu2_membase: dest:i src1:b len:12
-loadi4_membase: dest:i src1:b len:12
-loadu4_membase: dest:i src1:b len:12
-loadi8_membase: dest:i src1:b
-loadr4_membase: dest:f src1:b len:16
-loadr8_membase: dest:f src1:b len:20
+oparglist: src1:i len:64
+call: dest:o clob:c len:40
+call_reg: dest:o src1:i len:64 clob:c
+call_membase: dest:o src1:b len:64 clob:c
+voidcall: len:64 clob:c
+voidcall_reg: src1:i len:64 clob:c
+voidcall_membase: src1:b len:64 clob:c
+fcall: dest:f len:64 clob:c
+fcall_reg: dest:f src1:i len:64 clob:c
+fcall_membase: dest:f src1:b len:64 clob:c
+lcall: dest:l len:42 clob:c
+lcall_reg: dest:l src1:i len:64 clob:c
+lcall_membase: dest:l src1:b len:64 clob:c
+vcall: len:40 clob:c
+vcall_reg: src1:i len:64 clob:c
+vcall_membase: src1:b len:64 clob:c
+iconst: dest:i len:64
+i8const: dest:i len:64
+r4const: dest:f len:64
+r8const: dest:f len:64
+store_membase_imm: dest:b len:64
+store_membase_reg: dest:b src1:i len:64
+storei1_membase_imm: dest:b len:64
+storei1_membase_reg: dest:b src1:i len:64
+storei2_membase_imm: dest:b len:64
+storei2_membase_reg: dest:b src1:i len:64
+storei4_membase_imm: dest:b len:64
+storei4_membase_reg: dest:b src1:i len:64
+storei8_membase_imm: dest:b len:64 len:64
+storei8_membase_reg: dest:b src1:i len:64
+storer4_membase_reg: dest:b src1:f len:64
+storer8_membase_reg: dest:b src1:f len:64
+load_membase: dest:i src1:b len:64
+loadi1_membase: dest:i src1:b len:64
+loadu1_membase: dest:i src1:b len:64
+loadi2_membase: dest:i src1:b len:64
+loadu2_membase: dest:i src1:b len:64
+loadi4_membase: dest:i src1:b len:64
+loadu4_membase: dest:i src1:b len:64
+loadi8_membase: dest:i src1:b len:64
+loadr4_membase: dest:f src1:b len:64
+loadr8_membase: dest:f src1:b len:64
 loadu4_mem: dest:i len:8
 move: dest:i src1:i len:4
-add_imm: dest:i src1:i len:12
-sub_imm: dest:i src1:i len:12
-mul_imm: dest:i src1:i len:12
-div_imm: dest:a src1:i src2:i len:20
-div_un_imm: dest:a src1:i src2:i len:12
-rem_imm: dest:d src1:i src2:i len:20
-rem_un_imm: dest:d src1:i src2:i len:16
-and_imm: dest:i src1:i len:12
-or_imm: dest:i src1:i len:12
-xor_imm: dest:i src1:i len:12
-shl_imm: dest:i src1:i len:12
-shr_imm: dest:i src1:i len:12
-shr_un_imm: dest:i src1:i len:12
-cond_exc_eq: len:8
-cond_exc_ne_un: len:8
-cond_exc_lt: len:8
-cond_exc_lt_un: len:8
-cond_exc_gt: len:8
-cond_exc_gt_un: len:8
-cond_exc_ge: len:8
-cond_exc_ge_un: len:8
-cond_exc_le: len:8
-cond_exc_le_un: len:8
-cond_exc_ov: len:8
-cond_exc_no: len:8
-cond_exc_c: len:8
-cond_exc_nc: len:8
-long_add:
-long_sub:
-long_mul:
-long_div:
-long_div_un:
-long_rem:
-long_rem_un:
-long_and:
-long_or:
-long_xor:
-long_shl:
-long_shr:
-long_shr_un:
-long_neg:
-long_not:
-long_conv_to_i1:
-long_conv_to_i2:
-long_conv_to_i4:
-long_conv_to_i8:
-long_conv_to_r4:
-long_conv_to_r8:
-long_conv_to_u4:
-long_conv_to_u8:
-long_conv_to_u2:
-long_conv_to_u1:
-long_conv_to_i:
-long_conv_to_ovf_i: dest:i src1:i src2:i len:36
-long_conv_to_ovf_u:
-long_add_ovf:
-long_add_ovf_un:
-long_mul_ovf: 
-long_mul_ovf_un:
-long_sub_ovf:
-long_sub_ovf_un:
-long_conv_to_ovf_i1_un:
-long_conv_to_ovf_i2_un:
-long_conv_to_ovf_i4_un:
-long_conv_to_ovf_i8_un:
-long_conv_to_ovf_u1_un:
-long_conv_to_ovf_u2_un:
-long_conv_to_ovf_u4_un:
-long_conv_to_ovf_u8_un:
-long_conv_to_ovf_i_un:
-long_conv_to_ovf_u_un:
-long_conv_to_ovf_i1:
-long_conv_to_ovf_u1:
-long_conv_to_ovf_i2:
-long_conv_to_ovf_u2:
-long_conv_to_ovf_i4:
-long_conv_to_ovf_u4:
-long_conv_to_ovf_i8:
-long_conv_to_ovf_u8:
-long_ceq:
-long_cgt:
-long_cgt_un:
-long_clt:
-long_clt_un:
-long_conv_to_r_un: dest:f src1:i src2:i len:37 
-long_conv_to_u:
-long_shr_imm:
-long_shr_un_imm:
-long_shl_imm:
-long_add_imm:
-long_sub_imm:
-long_beq:
-long_bne_un:
-long_blt:
-long_blt_un:
-long_bgt:
-long_btg_un:
-long_bge:
-long_bge_un:
-long_ble:
-long_ble_un:
+add_imm: dest:i src1:i len:64
+addcc_imm: dest:i src1:i len:64
+sub_imm: dest:i src1:i len:64
+subcc_imm: dest:i src1:i len:64
+mul_imm: dest:i src1:i len:64
+div_imm: dest:a src1:i src2:i len:64
+div_un_imm: dest:a src1:i src2:i len:64
+rem_imm: dest:d src1:i src2:i len:64
+rem_un_imm: dest:d src1:i src2:i len:64
+and_imm: dest:i src1:i len:64
+or_imm: dest:i src1:i len:64
+xor_imm: dest:i src1:i len:64
+shl_imm: dest:i src1:i len:64
+shr_imm: dest:i src1:i len:64
+shr_un_imm: dest:i src1:i len:64
+cond_exc_eq: len:64
+cond_exc_ne_un: len:64
+cond_exc_lt: len:64
+cond_exc_lt_un: len:64
+cond_exc_gt: len:64
+cond_exc_gt_un: len:64
+cond_exc_ge: len:64
+cond_exc_ge_un: len:64
+cond_exc_le: len:64
+cond_exc_le_un: len:64
+cond_exc_ov: len:64
+cond_exc_no: len:64
+cond_exc_c: len:64
+cond_exc_nc: len:64
 float_beq: len:8
-float_bne_un: len:16
+float_bne_un: len:64
 float_blt: len:8
-float_blt_un: len:16
+float_blt_un: len:64
 float_bgt: len:8
-float_btg_un: len:16
-float_bge: len:16
-float_bge_un: len:16
-float_ble: len:16
-float_ble_un: len:16
+float_bgt_un: len:64
+float_bge: len:64
+float_bge_un: len:64
+float_ble: len:64
+float_ble_un: len:64
 float_add: dest:f src1:f src2:f len:4
 float_sub: dest:f src1:f src2:f len:4
 float_mul: dest:f src1:f src2:f len:4
 float_div: dest:f src1:f src2:f len:4
 float_div_un: dest:f src1:f src2:f len:4
-float_rem: dest:f src1:f src2:f len:16
-float_rem_un: dest:f src1:f src2:f len:16
+float_rem: dest:f src1:f src2:f len:64
+float_rem_un: dest:f src1:f src2:f len:64
 float_neg: dest:f src1:f len:4
 float_not: dest:f src1:f len:4
 float_conv_to_i1: dest:i src1:f len:40
 float_conv_to_i2: dest:i src1:f len:40
 float_conv_to_i4: dest:i src1:f len:40
-float_conv_to_i8: dest:l src1:f len:40
-float_conv_to_r4:
-float_conv_to_r8:
+float_conv_to_i8: dest:L src1:f len:40
+float_conv_to_r4: dest:f src1:f len:8
 float_conv_to_u4: dest:i src1:f len:40
-float_conv_to_u8: dest:l src1:f len:40
+float_conv_to_u8: dest:L src1:f len:40
 float_conv_to_u2: dest:i src1:f len:40
 float_conv_to_u1: dest:i src1:f len:40
 float_conv_to_i: dest:i src1:f len:40
-float_conv_to_ovf_i:
-float_conv_to_ovd_u:
-float_add_ovf:
-float_add_ovf_un:
-float_mul_ovf:
-float_mul_ovf_un:
-float_sub_ovf:
-float_sub_ovf_un:
-float_conv_to_ovf_i1_un:
-float_conv_to_ovf_i2_un:
-float_conv_to_ovf_i4_un:
-float_conv_to_ovf_i8_un:
-float_conv_to_ovf_u1_un:
-float_conv_to_ovf_u2_un:
-float_conv_to_ovf_u4_un:
-float_conv_to_ovf_u8_un:
-float_conv_to_ovf_i_un:
-float_conv_to_ovf_u_un:
-float_conv_to_ovf_i1:
-float_conv_to_ovf_u1:
-float_conv_to_ovf_i2:
-float_conv_to_ovf_u2:
-float_conv_to_ovf_i4:
-float_conv_to_ovf_u4:
-float_conv_to_ovf_i8:
-float_conv_to_ovf_u8:
-float_ceq: dest:i src1:f src2:f len:16
-float_cgt: dest:i src1:f src2:f len:16
-float_cgt_un: dest:i src1:f src2:f len:24
-float_clt: dest:i src1:f src2:f len:16
-float_clt_un: dest:i src1:f src2:f len:24
-float_conv_to_u: dest:i src1:f len:36
-call_handler: len:12
-op_endfilter: src1:i len:12
-aot_const: dest:i len:8
-x86_test_null: src1:i len:4
-x86_compare_membase_reg: src1:b src2:i len:8
-x86_compare_membase_imm: src1:b len:8
-x86_compare_reg_membase: src1:i src2:b len:8
-x86_inc_reg: dest:i src1:i clob:1 len:1
-x86_inc_membase: src1:b len:6
-x86_dec_reg: dest:i src1:i clob:1 len:1
-x86_dec_membase: src1:b len:6
-x86_add_membase_imm: src1:b len:8
-x86_sub_membase_imm: src1:b len:8
-x86_push: src1:i len:1
-x86_push_imm: len:5
-x86_push_membase: src1:b len:6
-x86_push_obj: src1:b len:30
-x86_lea: dest:i src1:i src2:i len:7
-x86_xchg: src1:i src2:i clob:x len:1
-x86_fpop: src1:f len:2
-x86_fp_load_i8: dest:f src1:b len:7
-x86_fp_load_i4: dest:f src1:b len:7
+float_ceq: dest:i src1:f src2:f len:64
+float_cgt: dest:i src1:f src2:f len:64
+float_cgt_un: dest:i src1:f src2:f len:64
+float_clt: dest:i src1:f src2:f len:64
+float_clt_un: dest:i src1:f src2:f len:64
+float_conv_to_u: dest:i src1:f len:64
+call_handler: len:64
+aot_const: dest:i len:64
 adc: dest:i src1:i src2:i len:4
 addcc: dest:i src1:i src2:i len:4
 subcc: dest:i src1:i src2:i len:4
-adc_imm: dest:i src1:i len:8
+adc_imm: dest:i src1:i len:64
 sbb: dest:i src1:i src2:i len:4
-sbb_imm: dest:i src1:i len:8
+sbb_imm: dest:i src1:i len:64
 br_reg: src1:i len:8
-ppc_subfic: dest:i src1:i len:4
-ppc_subfze: dest:i src1:i len:4
-op_bigmul: len:2 dest:l src1:a src2:i
-op_bigmul_un: len:2 dest:l src1:a src2:i
+bigmul: len:2 dest:L src1:a src2:i
+bigmul_un: len:2 dest:L src1:a src2:i
 fmove: dest:f src1:f len:8
 
+# 32 bit opcodes
+int_add: dest:i src1:i src2:i len:64
+int_sub: dest:i src1:i src2:i len:64
+int_mul: dest:i src1:i src2:i len:64
+int_div: dest:i src1:i src2:i len:64
+int_div_un: dest:i src1:i src2:i len:64
+int_rem: dest:i src1:i src2:i len:64
+int_rem_un: dest:i src1:i src2:i len:64
+int_and: dest:i src1:i src2:i len:64
+int_or: dest:i src1:i src2:i len:64
+int_xor: dest:i src1:i src2:i len:64
+int_shl: dest:i src1:i src2:i len:64
+int_shr: dest:i src1:i src2:i len:64
+int_shr_un: dest:i src1:i src2:i len:64
+int_adc: dest:i src1:i src2:i len:64
+int_adc_imm: dest:i src1:i len:64
+int_sbb: dest:i src1:i src2:i len:64
+int_sbb_imm: dest:i src1:i len:64
+int_addcc: dest:i src1:i src2:i len:64
+int_subcc: dest:i src1:i src2:i len:64
+int_add_imm: dest:i src1:i len:64
+int_sub_imm: dest:i src1:i len:64
+int_mul_imm: dest:i src1:i len:64
+int_div_imm: dest:i src1:i len:64
+int_div_un_imm: dest:i src1:i len:64
+int_rem_imm: dest:i src1:i len:64
+int_rem_un_imm: dest:i src1:i len:64
+int_and_imm: dest:i src1:i len:64
+int_or_imm: dest:i src1:i len:64
+int_xor_imm: dest:i src1:i len:64
+int_shl_imm: dest:i src1:i len:64
+int_shr_imm: dest:i src1:i len:64
+int_shr_un_imm: dest:i src1:i len:64
+int_mul_ovf: dest:i src1:i src2:i len:64
+int_mul_ovf_un: dest:i src1:i src2:i len:64
+int_conv_to_i1: dest:i src1:i len:8
+int_conv_to_i2: dest:i src1:i len:8
+int_conv_to_i4: dest:i src1:i len:4
+int_conv_to_i8: dest:i src1:i len:4
+int_conv_to_r4: dest:f src1:i len:64
+int_conv_to_r8: dest:f src1:i len:64
+int_conv_to_u4: dest:i src1:i len:4
+int_conv_to_u8: dest:i src1:i len:4
+int_conv_to_u2: dest:i src1:i len:8
+int_conv_to_u1: dest:i src1:i len:4
+int_conv_to_i: dest:i src1:i len:4
+int_neg: dest:i src1:i len:64
+int_not: dest:i src1:i len:64
+int_ceq: dest:i len:64
+int_cgt: dest:i len:64
+int_cgt_un: dest:i len:64
+int_clt: dest:i len:64
+int_clt_un: dest:i len:64
+int_beq: len:8
+int_bge: len:8
+int_bgt: len:8
+int_ble: len:8
+int_blt: len:8
+int_bne_un: len:64
+int_bge_un: len:64
+int_bgt_un: len:64
+int_ble_un: len:64
+int_blt_un: len:64
+
+# 64 bit opcodes
+long_shl: dest:i src1:i src2:i len:64
+long_shr: dest:i src1:i src2:i len:64
+long_shr_un: dest:i src1:i src2:i len:64
+long_conv_to_ovf_i: dest:i src1:i src2:i len:48
+long_mul_ovf: 
+long_conv_to_r_un: dest:f src1:i src2:i len:64 
+long_shr_imm: dest:i src1:i len:64
+long_shr_un_imm: dest:i src1:i len:64
+long_shl_imm: dest:i src1:i len:64
+
+memory_barrier: len:4
+
+sparc_brz: src1:i len: 8
+sparc_brlez: src1:i len: 8
+sparc_brlz: src1:i len: 8
+sparc_brnz: src1:i len: 8
+sparc_brgz: src1:i len: 8
+sparc_brgez: src1:i len: 8
+sparc_cond_exc_eqz: src1:i len:64
+sparc_cond_exc_nez: src1:i len:64
+sparc_cond_exc_ltz: src1:i len:64
+sparc_cond_exc_gtz: src1:i len:64
+sparc_cond_exc_gez: src1:i len:64
+sparc_cond_exc_lez: src1:i len:64
+
+relaxed_nop: len:0
+
+# Linear IR opcodes
+nop: len:0
+dummy_use: len:0
+dummy_store: len:0
+not_reached: len:0
+not_null: src1:i len:0
+
+jump_table: dest:i len:64
+
+cond_exc_ieq: len:64
+cond_exc_ine_un: len:64
+cond_exc_ilt: len:64
+cond_exc_ilt_un: len:64
+cond_exc_igt: len:64
+cond_exc_igt_un: len:64
+cond_exc_ige: len:64
+cond_exc_ige_un: len:64
+cond_exc_ile: len:64
+cond_exc_ile_un: len:64
+cond_exc_iov: len:64
+cond_exc_ino: len:64
+cond_exc_ic: len:64
+cond_exc_inc: len:64
+
+long_conv_to_ovf_i4_2: dest:i src1:i src2:i len:48
+
+vcall2: len:40 clob:c
+vcall2_reg: src1:i len:64 clob:c
+vcall2_membase: src1:b len:64 clob:c