X-Git-Url: http://wien.tomnetworks.com/gitweb/?a=blobdiff_plain;f=mono%2Fmini%2Fcpu-arm64.md;h=a8eea0965d54bb34f9263672de5063974c378e48;hb=dfac8517b91687f11479801fa0a2191585b1ad4c;hp=97e063f111ab26e24715bfb44957ddbd57ab6031;hpb=7551802f99c1baa48d83380520c01cfe42ed5a35;p=mono.git

diff --git a/mono/mini/cpu-arm64.md b/mono/mini/cpu-arm64.md
index 97e063f111a..a8eea0965d5 100644
--- a/mono/mini/cpu-arm64.md
+++ b/mono/mini/cpu-arm64.md
@@ -1,5 +1,6 @@
 # Copyright 2011-2013 Xamarin, Inc (http://www.xamarin.com)
 # Copyright 2003-2011 Novell, Inc (http://www.novell.com)
+# Licensed under the MIT license. See LICENSE file in the project root for full license information.
 # arm64 cpu description file
 # this file is read by genmdesc to pruduce a table with all the relevant information
 # about the cpu instructions that may be used by the regsiter allocator, the scheduler
@@ -56,7 +57,7 @@ br: len:16
 switch: src1:i len:12
 # See the comment in resume_from_signal_handler, we can't copy the fp regs from sigctx to MonoContext on linux,
 # since the corresponding sigctx structures are not well defined.
-seq_point: len:38 clob:c
+seq_point: len:40 clob:c
 il_seq_point: len:0
 
 throw: src1:i len:24
@@ -65,6 +66,7 @@ start_handler: len:32
 endfinally: len:32
 call_handler: len:16 clob:c
 endfilter: src1:i len:32
+get_ex_obj: dest:i len:16
 
 ckfinite: dest:f src1:f len:64
 ceq: dest:i len:12
@@ -76,6 +78,7 @@ localloc: dest:i src1:i len:96
 compare: src1:i src2:i len:4
 compare_imm: src1:i len:20
 fcompare: src1:f src2:f len:12
+rcompare: src1:f src2:f len:12
 oparglist: src1:i len:12
 setlret: src1:i src2:i len:12
 checkthis: src1:b len:4
@@ -88,6 +91,9 @@ voidcall_membase: src1:b len:32 clob:c
 fcall: dest:f len:32 clob:c
 fcall_reg: dest:f src1:i len:32 clob:c
 fcall_membase: dest:f src1:b len:32 clob:c
+rcall: dest:f len:32 clob:c
+rcall_reg: dest:f src1:i len:32 clob:c
+rcall_membase: dest:f src1:b len:32 clob:c
 lcall: dest:l len:32 clob:c
 lcall_reg: dest:l src1:i len:32 clob:c
 lcall_membase: dest:l src1:b len:32 clob:c
@@ -132,6 +138,11 @@ loadu4_memindex: dest:i src1:b src2:i len:4
 loadu4_mem: dest:i len:8
 move: dest:i src1:i len:4
 fmove: dest:f src1:f len:4
+rmove: dest:f src1:f len:4
+move_f_to_i4: dest:i src1:f len:8
+move_i4_to_f: dest:f src1:i len:8
+move_f_to_i8: dest:i src1:f len:4
+move_i8_to_f: dest:f src1:i len:4
 add_imm: dest:i src1:i len:12
 sub_imm: dest:i src1:i len:12
 mul_imm: dest:i src1:i len:12
@@ -194,6 +205,33 @@ float_cge: dest:i src1:f src2:f len:20
 float_cle: dest:i src1:f src2:f len:20
 float_conv_to_u: dest:i src1:f len:36
 setfret: src1:f len:12
+
+# R4 opcodes
+r4_conv_to_i1: dest:i src1:f len:8
+r4_conv_to_u1: dest:i src1:f len:8
+r4_conv_to_i2: dest:i src1:f len:8
+r4_conv_to_u2: dest:i src1:f len:8
+r4_conv_to_i4: dest:i src1:f len:8
+r4_conv_to_u4: dest:i src1:f len:8
+r4_conv_to_i8: dest:l src1:f len:8
+r4_conv_to_u8: dest:l src1:f len:8
+r4_conv_to_r4: dest:f src1:f len:4
+r4_conv_to_r8: dest:f src1:f len:4
+r4_add: dest:f src1:f src2:f len:4
+r4_sub: dest:f src1:f src2:f len:4
+r4_mul: dest:f src1:f src2:f len:4
+r4_div: dest:f src1:f src2:f len:4
+r4_rem: dest:f src1:f src2:f len:16
+r4_neg: dest:f src1:f len:4
+r4_ceq: dest:i src1:f src2:f len:16
+r4_cgt: dest:i src1:f src2:f len:16
+r4_cgt_un: dest:i src1:f src2:f len:20
+r4_clt: dest:i src1:f src2:f len:16
+r4_clt_un: dest:i src1:f src2:f len:20
+r4_cneq: dest:i src1:f src2:f len:20
+r4_cge: dest:i src1:f src2:f len:20
+r4_cle: dest:i src1:f src2:f len:20
+
 aot_const: dest:i len:16
 objc_get_selector: dest:i len:32
 sqrt: dest:f src1:f len:4
@@ -441,3 +479,6 @@ atomic_store_i8: dest:b src1:i len:12
 atomic_store_u8: dest:b src1:i len:12
 atomic_store_r4: dest:b src1:f len:24
 atomic_store_r8: dest:b src1:f len:20
+
+generic_class_init: src1:a len:44 clob:c
+gc_safe_point: src1:i len:12 clob:c