X-Git-Url: http://wien.tomnetworks.com/gitweb/?a=blobdiff_plain;f=mono%2Fmini%2Fcpu-arm.md;h=4b961766993e47c9e8406406a521ce0d78f9eb70;hb=866ada23cff1594587760abe7c10e89dfad0ac5b;hp=e0caf92fed15150940c08210d2ec06d2e5ca820d;hpb=d67ad1698bd2be2d7b1c54468dfc4f49a366798f;p=mono.git

diff --git a/mono/mini/cpu-arm.md b/mono/mini/cpu-arm.md
index e0caf92fed1..4b961766993 100644
--- a/mono/mini/cpu-arm.md
+++ b/mono/mini/cpu-arm.md
@@ -1,3 +1,5 @@
+# Copyright 2003-2011 Novell, Inc (http://www.novell.com)
+# Copyright 2011 Xamarin, Inc (http://www.xamarin.com)
 # arm cpu description file
 # this file is read by genmdesc to pruduce a table with all the relevant information
 # about the cpu instructions that may be used by the regsiter allocator, the scheduler
@@ -46,19 +48,20 @@
 #
 # See the code in mini-x86.c for more details on how the specifiers are used.
 #
-memory_barrier: len:4
+memory_barrier: len:8 clob:a
 nop: len:4
 relaxed_nop: len:4
 break: len:4
 jmp: len:92
 br: len:4
 switch: src1:i len:8
+seq_point: len:38
 
 throw: src1:i len:24
 rethrow: src1:i len:20
 start_handler: len:20
 endfinally: len:20
-call_handler: len:12
+call_handler: len:12 clob:c
 endfilter: src1:i len:16
 
 ckfinite: dest:f src1:f len:64
@@ -80,9 +83,9 @@ call_membase: dest:a src1:b len:12 clob:c
 voidcall: len:20 clob:c
 voidcall_reg: src1:i len:8 clob:c
 voidcall_membase: src1:b len:12 clob:c
-fcall: dest:g len:20 clob:c
-fcall_reg: dest:g src1:i len:8 clob:c
-fcall_membase: dest:g src1:b len:12 clob:c
+fcall: dest:g len:28 clob:c
+fcall_reg: dest:g src1:i len:16 clob:c
+fcall_membase: dest:g src1:b len:20 clob:c
 lcall: dest:l len:20 clob:c
 lcall_reg: dest:l src1:i len:8 clob:c
 lcall_membase: dest:l src1:b len:12 clob:c
@@ -90,7 +93,7 @@ vcall: len:20 clob:c
 vcall_reg: src1:i len:8 clob:c
 vcall_membase: src1:b len:12 clob:c
 iconst: dest:i len:16
-r4const: dest:f len:20
+r4const: dest:f len:24
 r8const: dest:f len:20
 label: len:0
 store_membase_imm: dest:b len:20
@@ -104,7 +107,7 @@ storei4_membase_reg: dest:b src1:i len:20
 storei8_membase_imm: dest:b 
 storei8_membase_reg: dest:b src1:i 
 storer4_membase_reg: dest:b src1:f len:12
-storer8_membase_reg: dest:b src1:f len:20
+storer8_membase_reg: dest:b src1:f len:24
 store_memindex: dest:b src1:i src2:i len:4
 storei1_memindex: dest:b src1:i src2:i len:4
 storei2_memindex: dest:b src1:i src2:i len:4
@@ -117,8 +120,8 @@ loadu2_membase: dest:i src1:b len:4
 loadi4_membase: dest:i src1:b len:4
 loadu4_membase: dest:i src1:b len:4
 loadi8_membase: dest:i src1:b
-loadr4_membase: dest:f src1:b len:4
-loadr8_membase: dest:f src1:b len:20
+loadr4_membase: dest:f src1:b len:8
+loadr8_membase: dest:f src1:b len:24
 load_memindex: dest:i src1:b src2:i len:4
 loadi1_memindex: dest:i src1:b src2:i len:4
 loadu1_memindex: dest:i src1:b src2:i len:4
@@ -132,10 +135,6 @@ fmove: dest:f src1:f len:4
 add_imm: dest:i src1:i len:12
 sub_imm: dest:i src1:i len:12
 mul_imm: dest:i src1:i len:12
-div_imm: dest:i src1:i src2:i len:20
-div_un_imm: dest:i src1:i src2:i len:12
-rem_imm: dest:i src1:i src2:i len:28
-rem_un_imm: dest:i src1:i src2:i len:16
 and_imm: dest:i src1:i len:12
 or_imm: dest:i src1:i len:12
 xor_imm: dest:i src1:i len:12
@@ -179,7 +178,7 @@ float_conv_to_i1: dest:i src1:f len:40
 float_conv_to_i2: dest:i src1:f len:40
 float_conv_to_i4: dest:i src1:f len:40
 float_conv_to_i8: dest:l src1:f len:40
-float_conv_to_r4: dest:f src1:f len:4
+float_conv_to_r4: dest:f src1:f len:8
 float_conv_to_u4: dest:i src1:f len:40
 float_conv_to_u8: dest:l src1:f len:40
 float_conv_to_u2: dest:i src1:f len:40
@@ -191,6 +190,7 @@ float_cgt_un: dest:i src1:f src2:f len:20
 float_clt: dest:i src1:f src2:f len:16
 float_clt_un: dest:i src1:f src2:f len:20
 float_conv_to_u: dest:i src1:f len:36
+setfret: src1:f len:12
 aot_const: dest:i len:16
 sqrt: dest:f src1:f len:4
 adc: dest:i src1:i src2:i len:4
@@ -204,7 +204,7 @@ sbb_imm: dest:i src1:i len:12
 br_reg: src1:i len:8
 bigmul: len:8 dest:l src1:i src2:i
 bigmul_un: len:8 dest:l src1:i src2:i
-tls_get: len:8 dest:i
+tls_get: len:8 dest:i clob:c
 
 # 32 bit opcodes
 int_add: dest:i src1:i src2:i len:4
@@ -252,13 +252,11 @@ sub_ovf_carry: dest:i src1:i src2:i len:16
 add_ovf_un_carry: dest:i src1:i src2:i len:16
 sub_ovf_un_carry: dest:i src1:i src2:i len:16
 
-long_conv_to_ovf_i: dest:i src1:i src2:i len:30
-
 arm_rsbs_imm: dest:i src1:i len:4
 arm_rsc_imm: dest:i src1:i len:4
 
 # Linear IR opcodes
-dummy_use: len:0
+dummy_use: src1:i len:0
 dummy_store: len:0
 not_reached: len:0
 not_null: src1:i len:0
@@ -313,6 +311,7 @@ long_conv_to_ovf_i4_2: dest:i src1:i src2:i len:36
 vcall2: len:20 clob:c
 vcall2_reg: src1:i len:8 clob:c
 vcall2_membase: src1:b len:12 clob:c
+dyn_call: src1:i src2:i len:120 clob:c
 
 # This is different from the original JIT opcodes
 float_beq: len:20
@@ -325,3 +324,10 @@ float_bge: len:20
 float_bge_un: len:20
 float_ble: len:20
 float_ble_un: len:20
+
+liverange_start: len:0
+liverange_end: len:0
+gc_liveness_def: len:0
+gc_liveness_use: len:0
+gc_spill_slot_liveness_def: len:0
+gc_param_slot_liveness_def: len:0