X-Git-Url: http://wien.tomnetworks.com/gitweb/?a=blobdiff_plain;f=mono%2Fmini%2Fcpu-arm.md;h=25e5f931118c65462120eb35e4050e4535ad5f88;hb=dc77e02244df98a8ae69aa7d7ff8888aa1fb3e32;hp=4e8edbc8d3e0cd421c415601a46e2fb4f04c7d04;hpb=cc40e2e17dc6fd2dae6d3a4c7d7ab43570d63546;p=mono.git

diff --git a/mono/mini/cpu-arm.md b/mono/mini/cpu-arm.md
index 4e8edbc8d3e..25e5f931118 100644
--- a/mono/mini/cpu-arm.md
+++ b/mono/mini/cpu-arm.md
@@ -1,5 +1,6 @@
 # Copyright 2003-2011 Novell, Inc (http://www.novell.com)
 # Copyright 2011 Xamarin, Inc (http://www.xamarin.com)
+# Licensed under the MIT license. See LICENSE file in the project root for full license information.
 # arm cpu description file
 # this file is read by genmdesc to pruduce a table with all the relevant information
 # about the cpu instructions that may be used by the regsiter allocator, the scheduler
@@ -15,7 +16,7 @@
 #
 # register may have the following values:
 #	i  integer register
-#	a  r3 register (output from calls)
+#	a  r0 register (first argument/result reg)
 #	b  base register (used in address references)
 #	f  floating point register
 #	g  floating point register returned in r0:r1 for soft-float mode
@@ -55,7 +56,7 @@ br: len:16
 switch: src1:i len:12
 # See the comment in resume_from_signal_handler, we can't copy the fp regs from sigctx to MonoContext on linux,
 # since the corresponding sigctx structures are not well defined.
-seq_point: len:38 clob:c
+seq_point: len:52 clob:c
 il_seq_point: len:0
 
 throw: src1:i len:24
@@ -82,22 +83,22 @@ setlret: src1:i src2:i len:12
 checkthis: src1:b len:4
 call: dest:a clob:c len:20
 call_reg: dest:a src1:i len:8 clob:c
-call_membase: dest:a src1:b len:24 clob:c
+call_membase: dest:a src1:b len:30 clob:c
 voidcall: len:20 clob:c
 voidcall_reg: src1:i len:8 clob:c
-voidcall_membase: src1:b len:16 clob:c
+voidcall_membase: src1:b len:24 clob:c
 fcall: dest:g len:28 clob:c
 fcall_reg: dest:g src1:i len:16 clob:c
-fcall_membase: dest:g src1:b len:24 clob:c
+fcall_membase: dest:g src1:b len:30 clob:c
 rcall: dest:g len:28 clob:c
 rcall_reg: dest:g src1:i len:16 clob:c
-rcall_membase: dest:g src1:b len:24 clob:c
+rcall_membase: dest:g src1:b len:30 clob:c
 lcall: dest:l len:20 clob:c
 lcall_reg: dest:l src1:i len:8 clob:c
-lcall_membase: dest:l src1:b len:16 clob:c
+lcall_membase: dest:l src1:b len:24 clob:c
 vcall: len:64 clob:c
 vcall_reg: src1:i len:64 clob:c
-vcall_membase: src1:b len:64 clob:c
+vcall_membase: src1:b len:70 clob:c
 tailcall: len:160 clob:c
 iconst: dest:i len:16
 r4const: dest:f len:24
@@ -204,6 +205,7 @@ float_cle: dest:y src1:f src2:f len:20
 float_conv_to_u: dest:i src1:f len:36
 
 # R4 opcodes
+rmove: dest:f src1:f len:4
 r4_conv_to_i1: dest:i src1:f len:88
 r4_conv_to_i2: dest:i src1:f len:88
 r4_conv_to_i4: dest:i src1:f len:88
@@ -242,7 +244,8 @@ sbb_imm: dest:i src1:i len:12
 br_reg: src1:i len:8
 bigmul: len:8 dest:l src1:i src2:i
 bigmul_un: len:8 dest:l src1:i src2:i
-tls_get: len:24 dest:i clob:c
+tls_get: len:16 dest:i
+tls_set: len:16 src1:i clob:c
 
 # 32 bit opcodes
 int_add: dest:i src1:i src2:i len:4
@@ -357,7 +360,7 @@ long_conv_to_ovf_i4_2: dest:i src1:i src2:i len:36
 vcall2: len:64 clob:c
 vcall2_reg: src1:i len:64 clob:c
 vcall2_membase: src1:b len:64 clob:c
-dyn_call: src1:i src2:i len:120 clob:c
+dyn_call: src1:i src2:i len:252 clob:c
 
 # This is different from the original JIT opcodes
 float_beq: len:32
@@ -377,6 +380,7 @@ gc_liveness_def: len:0
 gc_liveness_use: len:0
 gc_spill_slot_liveness_def: len:0
 gc_param_slot_liveness_def: len:0
+gc_safe_point: clob:c src1:i len:40
 
 atomic_add_i4: dest:i src1:i src2:i len:64
 atomic_exchange_i4: dest:i src1:i src2:i len:64
@@ -398,3 +402,5 @@ atomic_store_i4: dest:b src1:i len:28
 atomic_store_u4: dest:b src1:i len:28
 atomic_store_r4: dest:b src1:f len:80
 atomic_store_r8: dest:b src1:f len:32
+
+generic_class_init: src1:a len:44 clob:c