X-Git-Url: http://wien.tomnetworks.com/gitweb/?a=blobdiff_plain;f=mono%2Fmini%2Fcpu-arm.md;h=1909ba6e3ee68128fca8e7bbe24aad9d27f3f3b8;hb=92d89b2b067df5ee75533d956b69d42a3dfac611;hp=36b56fef9809cd14d08baaf7f3a4dfda3a5b816d;hpb=53e266903ec6b2d822cf5b0c566f6374df5307a4;p=mono.git

diff --git a/mono/mini/cpu-arm.md b/mono/mini/cpu-arm.md
index 36b56fef980..1909ba6e3ee 100644
--- a/mono/mini/cpu-arm.md
+++ b/mono/mini/cpu-arm.md
@@ -1,4 +1,6 @@
-# powerpc cpu description file
+# Copyright 2003-2011 Novell, Inc (http://www.novell.com)
+# Copyright 2011 Xamarin, Inc (http://www.xamarin.com)
+# arm cpu description file
 # this file is read by genmdesc to pruduce a table with all the relevant information
 # about the cpu instructions that may be used by the regsiter allocator, the scheduler
 # and other parts of the arch-dependent part of mini.
@@ -46,286 +48,56 @@
 #
 # See the code in mini-x86.c for more details on how the specifiers are used.
 #
-memory_barrier: len:4
+memory_barrier: len:8 clob:a
 nop: len:4
+relaxed_nop: len:4
 break: len:4
-ldarg.0:
-ldarg.1:
-ldarg.2:
-ldarg.3:
-ldloc.0:
-ldloc.1:
-ldloc.2:
-ldloc.3:
-stloc.0:
-stloc.1:
-stloc.2:
-stloc.3:
-ldarg.s:
-ldarga.s:
-starg.s:
-ldloc.s:
-ldloca.s:
-stloc.s:
-ldnull:
-ldc.i4.m1:
-ldc.i4.0:
-ldc.i4.1:
-ldc.i4.2:
-ldc.i4.3:
-ldc.i4.4:
-ldc.i4.5:
-ldc.i4.6:
-ldc.i4.7:
-ldc.i4.8:
-ldc.i4.s:
-ldc.i4:
-ldc.i8:
-ldc.r4:
-ldc.r8:
-dup:
-pop:
 jmp: len:92
-call: dest:a clob:c len:20
-calli:
-ret:
-br.s:
-brfalse.s:
-brtrue.s:
-beq.s:
-bge.s:
-bgt.s:
-ble.s:
-blt.s:
-bne.un.s:
-bge.un.s:
-bgt.un.s:
-ble.un.s:
-blt.un.s:
 br: len:4
-brfalse:
-brtrue:
-beq: len:8
-bge: len:8
-bgt: len:8
-ble: len:8
-blt: len:8
-bne.un: len:8
-bge.un: len:8
-bgt.un: len:8
-ble.un: len:8
-blt.un: len:8
 switch: src1:i len:8
-ldind.i1: dest:i len:8
-ldind.u1: dest:i len:8
-ldind.i2: dest:i len:8
-ldind.u2: dest:i len:8
-ldind.i4: dest:i len:8
-ldind.u4: dest:i len:8
-ldind.i8:
-ldind.i: dest:i len:8
-ldind.r4:
-ldind.r8:
-ldind.ref: dest:i len:8
-stind.ref: src1:b src2:i
-stind.i1: src1:b src2:i
-stind.i2: src1:b src2:i
-stind.i4: src1:b src2:i
-stind.i8:
-stind.r4: src1:b src2:f
-stind.r8: src1:b src2:f
-add: dest:i src1:i src2:i len:4
-sub: dest:i src1:i src2:i len:4
-mul: dest:i src1:i src2:i len:4
-div: dest:i src1:i src2:i len:40
-div.un: dest:i src1:i src2:i len:16
-rem: dest:i src1:i src2:i len:48
-rem.un: dest:i src1:i src2:i len:24
-and: dest:i src1:i src2:i len:4
-or: dest:i src1:i src2:i len:4
-xor: dest:i src1:i src2:i len:4
-shl: dest:i src1:i src2:i len:4
-shr: dest:i src1:i src2:i len:4
-shr.un: dest:i src1:i src2:i len:4
-neg: dest:i src1:i len:4
-not: dest:i src1:i len:4
-conv.i1: dest:i src1:i len:8
-conv.i2: dest:i src1:i len:8
-conv.i4: dest:i src1:i len:4
-conv.i8:
-conv.r4: dest:f src1:i len:36
-conv.r8: dest:f src1:i len:36
-conv.u4: dest:i src1:i
-conv.u8:
-callvirt:
-cpobj:
-ldobj:
-ldstr:
-newobj:
-castclass:
-isinst:
-conv.r.un: dest:f src1:i len:56
-unbox:
-throw: src1:i len:20
-op_rethrow: src1:i len:20
-ldfld:
-ldflda:
-stfld:
-ldsfld:
-ldsflda:
-stsfld:
-stobj:
-conv.ovf.i1.un:
-conv.ovf.i2.un:
-conv.ovf.i4.un:
-conv.ovf.i8.un:
-conv.ovf.u1.un:
-conv.ovf.u2.un:
-conv.ovf.u4.un:
-conv.ovf.u8.un:
-conv.ovf.i.un:
-conv.ovf.u.un:
-box:
-newarr:
-ldlen:
-ldelema:
-ldelem.i1:
-ldelem.u1:
-ldelem.i2:
-ldelem.u2:
-ldelem.i4:
-ldelem.u4:
-ldelem.i8:
-ldelem.i:
-ldelem.r4:
-ldelem.r8:
-ldelem.ref:
-stelem.i:
-stelem.i1:
-stelem.i2:
-stelem.i4:
-stelem.i8:
-stelem.r4:
-stelem.r8:
-stelem.ref:
-conv.ovf.i1:
-conv.ovf.u1:
-conv.ovf.i2:
-conv.ovf.u2:
-conv.ovf.i4:
-conv.ovf.u4:
-conv.ovf.i8:
-conv.ovf.u8:
-refanyval:
-ckfinite: dest:f src1:f len:24
-mkrefany:
-ldtoken:
-conv.u2: dest:i src1:i len:8
-conv.u1: dest:i src1:i len:4
-conv.i: dest:i src1:i len:4
-conv.ovf.i:
-conv.ovf.u:
-add.ovf: dest:i src1:i src2:i len:16
-add.ovf.un: dest:i src1:i src2:i len:16
-mul.ovf: dest:i src1:i src2:i len:16
-# this opcode is handled specially in the code generator
-mul.ovf.un: dest:i src1:i src2:i len:16
-sub.ovf: dest:i src1:i src2:i len:16
-sub.ovf.un: dest:i src1:i src2:i len:16
-add_ovf_carry: dest:i src1:i src2:i len:16
-sub_ovf_carry: dest:i src1:i src2:i len:16
-add_ovf_un_carry: dest:i src1:i src2:i len:16
-sub_ovf_un_carry: dest:i src1:i src2:i len:16
+# See the comment in resume_from_signal_handler, we can't copy the fp regs from sigctx to MonoContext on linux,
+# since the corresponding sigctx structures are not well defined.
+seq_point: len:38 clob:c
+
+throw: src1:i len:24
+rethrow: src1:i len:20
 start_handler: len:20
 endfinally: len:20
-leave:
-leave.s:
-stind.i:
-conv.u: dest:i src1:i len:4
-prefix7:
-prefix6:
-prefix5:
-prefix4:
-prefix3:
-prefix2:
-prefix1:
-prefixref:
-arglist:
+call_handler: len:12 clob:c
+endfilter: src1:i len:16
+
+ckfinite: dest:f src1:f len:64
 ceq: dest:i len:12
 cgt: dest:i len:12
 cgt.un: dest:i len:12
 clt: dest:i len:12
 clt.un: dest:i len:12
-ldftn:
-ldvirtftn:
-ldarg:
-ldarga:
-starg:
-ldloc:
-ldloca:
-stloc:
 localloc: dest:i src1:i len:60
-endfilter: len:20
-unaligned.:
-volatile.:
-tail.:
-initobj:
-cpblk:
-initblk:
-rethrow:
-sizeof:
-refanytype:
-illegal:
-endmac:
-mono_objaddr:
-mono_ldptr:
-mono_vtaddr:
-mono_newobj:
-mono_retobj:
-load:
-ldaddr:
-store:
-phi:
-rename:
 compare: src1:i src2:i len:4
 compare_imm: src1:i len:12
 fcompare: src1:f src2:f len:12
-lcompare:
-local:
-arg:
 oparglist: src1:i len:12
-outarg: src1:i len:1
-outarg_imm: len:16
-retarg:
-setret: dest:a src1:i len:4
 setlret: src1:i src2:i len:12
-setreg: dest:i src1:i len:4 clob:r
-setregimm: dest:i len:16 clob:r
-setfreg: dest:f src1:f len:4 clob:r
 checkthis: src1:b len:4
+call: dest:a clob:c len:20
+call_reg: dest:a src1:i len:8 clob:c
+call_membase: dest:a src1:b len:12 clob:c
 voidcall: len:20 clob:c
 voidcall_reg: src1:i len:8 clob:c
 voidcall_membase: src1:b len:12 clob:c
-fcall: dest:g len:20 clob:c
-fcall_reg: dest:g src1:i len:8 clob:c
-fcall_membase: dest:g src1:b len:12 clob:c
+fcall: dest:g len:28 clob:c
+fcall_reg: dest:g src1:i len:16 clob:c
+fcall_membase: dest:g src1:b len:20 clob:c
 lcall: dest:l len:20 clob:c
 lcall_reg: dest:l src1:i len:8 clob:c
 lcall_membase: dest:l src1:b len:12 clob:c
 vcall: len:20 clob:c
 vcall_reg: src1:i len:8 clob:c
 vcall_membase: src1:b len:12 clob:c
-call_reg: dest:a src1:i len:8 clob:c
-call_membase: dest:a src1:b len:12 clob:c
-trap:
 iconst: dest:i len:16
-i8const:
-r4const: dest:f len:20
+r4const: dest:f len:24
 r8const: dest:f len:20
-regvar:
-reg:
-regoffset:
-label:
+label: len:0
 store_membase_imm: dest:b len:20
 store_membase_reg: dest:b src1:i len:20
 storei1_membase_imm: dest:b len:20
@@ -337,7 +109,7 @@ storei4_membase_reg: dest:b src1:i len:20
 storei8_membase_imm: dest:b 
 storei8_membase_reg: dest:b src1:i 
 storer4_membase_reg: dest:b src1:f len:12
-storer8_membase_reg: dest:b src1:f len:12
+storer8_membase_reg: dest:b src1:f len:24
 store_memindex: dest:b src1:i src2:i len:4
 storei1_memindex: dest:b src1:i src2:i len:4
 storei2_memindex: dest:b src1:i src2:i len:4
@@ -350,8 +122,8 @@ loadu2_membase: dest:i src1:b len:4
 loadi4_membase: dest:i src1:b len:4
 loadu4_membase: dest:i src1:b len:4
 loadi8_membase: dest:i src1:b
-loadr4_membase: dest:f src1:b len:4
-loadr8_membase: dest:f src1:b len:4
+loadr4_membase: dest:f src1:b len:8
+loadr8_membase: dest:f src1:b len:24
 load_memindex: dest:i src1:b src2:i len:4
 loadi1_memindex: dest:i src1:b src2:i len:4
 loadu1_memindex: dest:i src1:b src2:i len:4
@@ -365,13 +137,6 @@ fmove: dest:f src1:f len:4
 add_imm: dest:i src1:i len:12
 sub_imm: dest:i src1:i len:12
 mul_imm: dest:i src1:i len:12
-# there is no actual support for division or reminder by immediate
-# we simulate them, though (but we need to change the burg rules 
-# to allocate a symbolic reg for src2)
-div_imm: dest:i src1:i src2:i len:20
-div_un_imm: dest:i src1:i src2:i len:12
-rem_imm: dest:i src1:i src2:i len:28
-rem_un_imm: dest:i src1:i src2:i len:16
 and_imm: dest:i src1:i len:12
 or_imm: dest:i src1:i len:12
 xor_imm: dest:i src1:i len:12
@@ -392,90 +157,16 @@ cond_exc_ov: len:12
 cond_exc_no: len:8
 cond_exc_c: len:12
 cond_exc_nc: len:8
-long_add:
-long_sub:
-long_mul:
-long_div:
-long_div_un:
-long_rem:
-long_rem_un:
-long_and:
-long_or:
-long_xor:
-long_shl:
-long_shr:
-long_shr_un:
-long_neg:
-long_not:
-long_conv_to_i1:
-long_conv_to_i2:
-long_conv_to_i4:
-long_conv_to_i8:
-long_conv_to_r4:
-long_conv_to_r8:
-long_conv_to_u4:
-long_conv_to_u8:
-long_conv_to_u2:
-long_conv_to_u1:
-long_conv_to_i:
-long_conv_to_ovf_i: dest:i src1:i src2:i len:30
-long_conv_to_ovf_u:
-long_add_ovf:
-long_add_ovf_un:
-long_mul_ovf: 
-long_mul_ovf_un:
-long_sub_ovf:
-long_sub_ovf_un:
-long_conv_to_ovf_i1_un:
-long_conv_to_ovf_i2_un:
-long_conv_to_ovf_i4_un:
-long_conv_to_ovf_i8_un:
-long_conv_to_ovf_u1_un:
-long_conv_to_ovf_u2_un:
-long_conv_to_ovf_u4_un:
-long_conv_to_ovf_u8_un:
-long_conv_to_ovf_i_un:
-long_conv_to_ovf_u_un:
-long_conv_to_ovf_i1:
-long_conv_to_ovf_u1:
-long_conv_to_ovf_i2:
-long_conv_to_ovf_u2:
-long_conv_to_ovf_i4:
-long_conv_to_ovf_u4:
-long_conv_to_ovf_i8:
-long_conv_to_ovf_u8:
-long_ceq:
-long_cgt:
-long_cgt_un:
-long_clt:
-long_clt_un:
-long_conv_to_r_un: dest:f src1:i src2:i len:37 
-long_conv_to_u:
-long_shr_imm:
-long_shr_un_imm:
-long_shl_imm:
-long_add_imm:
-long_sub_imm:
-long_beq:
-long_bne_un:
-long_blt:
-long_blt_un:
-long_bgt:
-long_btg_un:
-long_bge:
-long_bge_un:
-long_ble:
-long_ble_un:
-float_beq: src1:f src2:f len:20
-float_bne_un: src1:f src2:f len:20
-float_blt: src1:f src2:f len:20
-float_blt_un: src1:f src2:f len:20
-float_bgt: src1:f src2:f len:20
-float_btg_un: src1:f src2:f len:20
-float_bge: src1:f src2:f len:20
-float_bge_un: src1:f src2:f len:20
-float_ble: src1:f src2:f len:20
-float_ble_un: src1:f src2:f len:20
+#float_beq: src1:f src2:f len:20
+#float_bne_un: src1:f src2:f len:20
+#float_blt: src1:f src2:f len:20
+#float_blt_un: src1:f src2:f len:20
+#float_bgt: src1:f src2:f len:20
+#float_bgt_un: src1:f src2:f len:20
+#float_bge: src1:f src2:f len:20
+#float_bge_un: src1:f src2:f len:20
+#float_ble: src1:f src2:f len:20
+#float_ble_un: src1:f src2:f len:20
 float_add: dest:f src1:f src2:f len:4
 float_sub: dest:f src1:f src2:f len:4
 float_mul: dest:f src1:f src2:f len:4
@@ -489,48 +180,20 @@ float_conv_to_i1: dest:i src1:f len:40
 float_conv_to_i2: dest:i src1:f len:40
 float_conv_to_i4: dest:i src1:f len:40
 float_conv_to_i8: dest:l src1:f len:40
-float_conv_to_r4: dest:f src1:f len:4
-float_conv_to_r8:
+float_conv_to_r4: dest:f src1:f len:8
 float_conv_to_u4: dest:i src1:f len:40
 float_conv_to_u8: dest:l src1:f len:40
 float_conv_to_u2: dest:i src1:f len:40
 float_conv_to_u1: dest:i src1:f len:40
 float_conv_to_i: dest:i src1:f len:40
-float_conv_to_ovf_i:
-float_conv_to_ovd_u:
-float_add_ovf:
-float_add_ovf_un:
-float_mul_ovf:
-float_mul_ovf_un:
-float_sub_ovf:
-float_sub_ovf_un:
-float_conv_to_ovf_i1_un:
-float_conv_to_ovf_i2_un:
-float_conv_to_ovf_i4_un:
-float_conv_to_ovf_i8_un:
-float_conv_to_ovf_u1_un:
-float_conv_to_ovf_u2_un:
-float_conv_to_ovf_u4_un:
-float_conv_to_ovf_u8_un:
-float_conv_to_ovf_i_un:
-float_conv_to_ovf_u_un:
-float_conv_to_ovf_i1:
-float_conv_to_ovf_u1:
-float_conv_to_ovf_i2:
-float_conv_to_ovf_u2:
-float_conv_to_ovf_i4:
-float_conv_to_ovf_u4:
-float_conv_to_ovf_i8:
-float_conv_to_ovf_u8:
 float_ceq: dest:i src1:f src2:f len:16
 float_cgt: dest:i src1:f src2:f len:16
 float_cgt_un: dest:i src1:f src2:f len:20
 float_clt: dest:i src1:f src2:f len:16
 float_clt_un: dest:i src1:f src2:f len:20
 float_conv_to_u: dest:i src1:f len:36
-call_handler: len:12
-op_endfilter: src1:i len:16
-aot_const: dest:i len:8
+setfret: src1:f len:12
+aot_const: dest:i len:16
 sqrt: dest:f src1:f len:4
 adc: dest:i src1:i src2:i len:4
 addcc: dest:i src1:i src2:i len:4
@@ -541,8 +204,132 @@ subcc_imm: dest:i src1:i len:12
 sbb: dest:i src1:i src2:i len:4
 sbb_imm: dest:i src1:i len:12
 br_reg: src1:i len:8
+bigmul: len:8 dest:l src1:i src2:i
+bigmul_un: len:8 dest:l src1:i src2:i
+tls_get: len:8 dest:i clob:c
+
+# 32 bit opcodes
+int_add: dest:i src1:i src2:i len:4
+int_sub: dest:i src1:i src2:i len:4
+int_mul: dest:i src1:i src2:i len:4
+int_div: dest:i src1:i src2:i len:40
+int_div_un: dest:i src1:i src2:i len:16
+int_rem: dest:i src1:i src2:i len:48
+int_rem_un: dest:i src1:i src2:i len:24
+int_and: dest:i src1:i src2:i len:4
+int_or: dest:i src1:i src2:i len:4
+int_xor: dest:i src1:i src2:i len:4
+int_shl: dest:i src1:i src2:i len:4
+int_shr: dest:i src1:i src2:i len:4
+int_shr_un: dest:i src1:i src2:i len:4
+int_neg: dest:i src1:i len:4
+int_not: dest:i src1:i len:4
+int_conv_to_i1: dest:i src1:i len:8
+int_conv_to_i2: dest:i src1:i len:8
+int_conv_to_i4: dest:i src1:i len:4
+int_conv_to_r4: dest:f src1:i len:36
+int_conv_to_r8: dest:f src1:i len:36
+int_conv_to_u4: dest:i src1:i
+int_conv_to_r_un: dest:f src1:i len:56
+int_conv_to_u2: dest:i src1:i len:8
+int_conv_to_u1: dest:i src1:i len:4
+int_beq: len:8
+int_bge: len:8
+int_bgt: len:8
+int_ble: len:8
+int_blt: len:8
+int_bne_un: len:8
+int_bge_un: len:8
+int_bgt_un: len:8
+int_ble_un: len:8
+int_blt_un: len:8
+int_add_ovf: dest:i src1:i src2:i len:16
+int_add_ovf_un: dest:i src1:i src2:i len:16
+int_mul_ovf: dest:i src1:i src2:i len:16
+int_mul_ovf_un: dest:i src1:i src2:i len:16
+int_sub_ovf: dest:i src1:i src2:i len:16
+int_sub_ovf_un: dest:i src1:i src2:i len:16
+add_ovf_carry: dest:i src1:i src2:i len:16
+sub_ovf_carry: dest:i src1:i src2:i len:16
+add_ovf_un_carry: dest:i src1:i src2:i len:16
+sub_ovf_un_carry: dest:i src1:i src2:i len:16
+
 arm_rsbs_imm: dest:i src1:i len:4
 arm_rsc_imm: dest:i src1:i len:4
-op_bigmul: len:8 dest:l src1:i src2:i
-op_bigmul_un: len:8 dest:l src1:i src2:i
-tls_get: len:8 dest:i
+
+# Linear IR opcodes
+dummy_use: src1:i len:0
+dummy_store: len:0
+not_reached: len:0
+not_null: src1:i len:0
+
+int_adc: dest:i src1:i src2:i len:4
+int_addcc: dest:i src1:i src2:i len:4
+int_subcc: dest:i src1:i src2:i len:4
+int_sbb: dest:i src1:i src2:i len:4
+int_adc_imm: dest:i src1:i len:12
+int_sbb_imm: dest:i src1:i len:12
+
+int_add_imm: dest:i src1:i len:12
+int_sub_imm: dest:i src1:i len:12
+int_mul_imm: dest:i src1:i len:12
+int_div_imm: dest:i src1:i len:20
+int_div_un_imm: dest:i src1:i len:12
+int_rem_imm: dest:i src1:i len:28
+int_rem_un_imm: dest:i src1:i len:16
+int_and_imm: dest:i src1:i len:12
+int_or_imm: dest:i src1:i len:12
+int_xor_imm: dest:i src1:i len:12
+int_shl_imm: dest:i src1:i len:8
+int_shr_imm: dest:i src1:i len:8
+int_shr_un_imm: dest:i src1:i len:8
+
+int_ceq: dest:i len:12
+int_cgt: dest:i len:12
+int_cgt_un: dest:i len:12
+int_clt: dest:i len:12
+int_clt_un: dest:i len:12
+
+cond_exc_ieq: len:8
+cond_exc_ine_un: len:8
+cond_exc_ilt: len:8
+cond_exc_ilt_un: len:8
+cond_exc_igt: len:8
+cond_exc_igt_un: len:8
+cond_exc_ige: len:8
+cond_exc_ige_un: len:8
+cond_exc_ile: len:8
+cond_exc_ile_un: len:8
+cond_exc_iov: len:12
+cond_exc_ino: len:8
+cond_exc_ic: len:12
+cond_exc_inc: len:8
+
+icompare: src1:i src2:i len:4
+icompare_imm: src1:i len:12
+
+long_conv_to_ovf_i4_2: dest:i src1:i src2:i len:36
+
+vcall2: len:20 clob:c
+vcall2_reg: src1:i len:8 clob:c
+vcall2_membase: src1:b len:12 clob:c
+dyn_call: src1:i src2:i len:120 clob:c
+
+# This is different from the original JIT opcodes
+float_beq: len:20
+float_bne_un: len:20
+float_blt: len:20
+float_blt_un: len:20
+float_bgt: len:20
+float_bgt_un: len:20
+float_bge: len:20
+float_bge_un: len:20
+float_ble: len:20
+float_ble_un: len:20
+
+liverange_start: len:0
+liverange_end: len:0
+gc_liveness_def: len:0
+gc_liveness_use: len:0
+gc_spill_slot_liveness_def: len:0
+gc_param_slot_liveness_def: len:0