X-Git-Url: http://wien.tomnetworks.com/gitweb/?a=blobdiff_plain;f=mono%2Farch%2Fx86%2Fx86-codegen.h;h=8cf3e80223d65b59e210f8975da5bea64420b8b0;hb=c39145af2464b19374fac41b252e07480ae1a197;hp=83930b1c79df6ceebc5d88fa711431cd4f4492dc;hpb=8c993f32c2b4add7c9178003edbeb4a44e7b646e;p=mono.git diff --git a/mono/arch/x86/x86-codegen.h b/mono/arch/x86/x86-codegen.h index 83930b1c79d..8cf3e80223d 100644 --- a/mono/arch/x86/x86-codegen.h +++ b/mono/arch/x86/x86-codegen.h @@ -1,8 +1,16 @@ -/* Copyright (C) 2000 Intel Corporation. All rights reserved. - Copyright (C) 2001 Ximian, Inc. -// -// $Header: /home/miguel/third-conversion/public/mono/mono/arch/x86/x86-codegen.h,v 1.27 2002/05/03 12:52:19 lupus Exp $ -*/ +/* + * x86-codegen.h: Macros for generating x86 code + * + * Authors: + * Paolo Molaro (lupus@ximian.com) + * Intel Corporation (ORP Project) + * Sergey Chaban (serge@wildwestsoftware.com) + * Dietmar Maurer (dietmar@ximian.com) + * Patrik Torstensson + * + * Copyright (C) 2000 Intel Corporation. All rights reserved. + * Copyright (C) 2001, 2002 Ximian, Inc. + */ #ifndef X86_H #define X86_H @@ -41,6 +49,10 @@ typedef enum { typedef enum { X86_SHLD, X86_SHLR, + X86_ROL = 0, + X86_ROR = 1, + X86_RCL = 2, + X86_RCR = 3, X86_SHL = 4, X86_SHR = 5, X86_SAR = 7, @@ -78,6 +90,39 @@ typedef enum { X86_CC_NO = 11, X86_NCC } X86_CC; + +/* FP status */ +enum { + X86_FP_C0 = 0x100, + X86_FP_C1 = 0x200, + X86_FP_C2 = 0x400, + X86_FP_C3 = 0x4000, + X86_FP_CC_MASK = 0x4500 +}; + +/* FP control word */ +enum { + X86_FPCW_INVOPEX_MASK = 0x1, + X86_FPCW_DENOPEX_MASK = 0x2, + X86_FPCW_ZERODIV_MASK = 0x4, + X86_FPCW_OVFEX_MASK = 0x8, + X86_FPCW_UNDFEX_MASK = 0x10, + X86_FPCW_PRECEX_MASK = 0x20, + X86_FPCW_PRECC_MASK = 0x300, + X86_FPCW_ROUNDC_MASK = 0xc00, + + /* values for precision control */ + X86_FPCW_PREC_SINGLE = 0, + X86_FPCW_PREC_DOUBLE = 0x200, + X86_FPCW_PREC_EXTENDED = 0x300, + + /* values for rounding control */ + X86_FPCW_ROUND_NEAREST = 0, + X86_FPCW_ROUND_DOWN = 0x400, + X86_FPCW_ROUND_UP = 0x800, + X86_FPCW_ROUND_TOZERO = 0xc00 +}; + /* // prefix code */ @@ -92,6 +137,8 @@ typedef enum { X86_ES_PREFIX = 0x26, X86_FS_PREFIX = 0x64, X86_GS_PREFIX = 0x65, + X86_UNLIKELY_PREFIX = 0x2E, + X86_LIKELY_PREFIX = 0x3E, X86_OPERAND_PREFIX = 0x66, X86_ADDRESS_PREFIX = 0x67 } X86_Prefix; @@ -150,6 +197,8 @@ typedef union { #define X86_IS_SCRATCH(reg) (X86_CALLER_REGS & (1 << (reg))) /* X86_EAX, X86_ECX, or X86_EDX */ #define X86_IS_CALLEE(reg) (X86_CALLEE_REGS & (1 << (reg))) /* X86_ESI, X86_EDI, X86_EBX, or X86_EBP */ +#define X86_IS_BYTE_REG(reg) ((reg) < 4) + /* // Frame structure: // @@ -193,6 +242,10 @@ typedef union { /* * useful building blocks */ +#define x86_modrm_mod(modrm) ((modrm) >> 6) +#define x86_modrm_reg(modrm) (((modrm) >> 3) & 0x7) +#define x86_modrm_rm(modrm) ((modrm) & 0x7) + #define x86_address_byte(inst,m,o,r) do { *(inst)++ = ((((m)&0x03)<<6)|(((o)&0x07)<<3)|(((r)&0x07))); } while (0) #define x86_imm_emit32(inst,imm) \ do { \ @@ -208,6 +261,7 @@ typedef union { #define x86_is_imm16(imm) (((int)(imm) >= -(1<<16) && (int)(imm) <= ((1<<16)-1))) #define x86_reg_emit(inst,r,regno) do { x86_address_byte ((inst), 3, (r), (regno)); } while (0) +#define x86_reg8_emit(inst,r,regno,is_rh,is_rnoh) do {x86_address_byte ((inst), 3, (is_rh)?((r)|4):(r), (is_rnoh)?((regno)|4):(regno));} while (0) #define x86_regp_emit(inst,r,regno) do { x86_address_byte ((inst), 0, (r), (regno)); } while (0) #define x86_mem_emit(inst,r,disp) do { x86_address_byte ((inst), 0, (r), 5); x86_imm_emit32((inst), (disp)); } while (0) @@ -254,7 +308,7 @@ typedef union { x86_address_byte ((inst), (shift), (indexreg), (basereg)); \ x86_imm_emit8 ((inst), (disp)); \ } else { \ - x86_address_byte ((inst), 0, (r), 4); \ + x86_address_byte ((inst), 2, (r), 4); \ x86_address_byte ((inst), (shift), (indexreg), 5); \ x86_imm_emit32 ((inst), (disp)); \ } \ @@ -280,9 +334,9 @@ typedef union { do { \ unsigned char* pos = (ins) + 1; \ int disp, size = 0; \ - switch (*(ins)) { \ + switch (*(unsigned char*)(ins)) { \ case 0xe8: case 0xe9: ++size; break; /* call, jump32 */ \ - case 0x0f: if (!(*pos >= 0x70 && *pos <= 0x7f)) assert (0); \ + case 0x0f: if (!(*pos >= 0x70 && *pos <= 0x8f)) assert (0); \ ++size; ++pos; break; /* prefix for 32-bit disp */ \ case 0xe0: case 0xe1: case 0xe2: /* loop */ \ case 0xeb: /* jump8 */ \ @@ -296,7 +350,7 @@ typedef union { } \ disp = (target) - pos; \ if (size) x86_imm_emit32 (pos, disp - 4); \ - else if (x86_is_imm8 (disp)) x86_imm_emit8 (pos, disp - 1); \ + else if (x86_is_imm8 (disp - 1)) x86_imm_emit8 (pos, disp - 1); \ else assert (0); \ } while (0) @@ -308,6 +362,10 @@ typedef union { #define x86_cld(inst) do { *(inst)++ =(unsigned char)0xfc; } while (0) #define x86_stosb(inst) do { *(inst)++ =(unsigned char)0xaa; } while (0) #define x86_stosl(inst) do { *(inst)++ =(unsigned char)0xab; } while (0) +#define x86_stosd(inst) x86_stosl((inst)) +#define x86_movsb(inst) do { *(inst)++ =(unsigned char)0xa4; } while (0) +#define x86_movsl(inst) do { *(inst)++ =(unsigned char)0xa5; } while (0) +#define x86_movsd(inst) x86_movsl((inst)) #define x86_prefix(inst,p) do { *(inst)++ =(unsigned char) (p); } while (0) @@ -365,6 +423,36 @@ typedef union { x86_membase_emit ((inst), (reg), (basereg), (disp)); \ } while (0) +#define x86_xadd_reg_reg(inst,dreg,reg,size) \ + do { \ + *(inst)++ = (unsigned char)0x0F; \ + if ((size) == 1) \ + *(inst)++ = (unsigned char)0xC0; \ + else \ + *(inst)++ = (unsigned char)0xC1; \ + x86_reg_emit ((inst), (reg), (dreg)); \ + } while (0) + +#define x86_xadd_mem_reg(inst,mem,reg,size) \ + do { \ + *(inst)++ = (unsigned char)0x0F; \ + if ((size) == 1) \ + *(inst)++ = (unsigned char)0xC0; \ + else \ + *(inst)++ = (unsigned char)0xC1; \ + x86_mem_emit ((inst), (reg), (mem)); \ + } while (0) + +#define x86_xadd_membase_reg(inst,basereg,disp,reg,size) \ + do { \ + *(inst)++ = (unsigned char)0x0F; \ + if ((size) == 1) \ + *(inst)++ = (unsigned char)0xC0; \ + else \ + *(inst)++ = (unsigned char)0xC1; \ + x86_membase_emit ((inst), (reg), (basereg), (disp)); \ + } while (0) + #define x86_inc_mem(inst,mem) \ do { \ *(inst)++ = (unsigned char)0xff; \ @@ -474,6 +562,13 @@ typedef union { x86_imm_emit32 ((inst), (imm)); \ } \ } while (0) + +#define x86_alu_membase8_imm(inst,opc,basereg,disp,imm) \ + do { \ + *(inst)++ = (unsigned char)0x80; \ + x86_membase_emit ((inst), (opc), (basereg), (disp)); \ + x86_imm_emit8 ((inst), (imm)); \ + } while (0) #define x86_alu_mem_reg(inst,opc,mem,reg) \ do { \ @@ -493,6 +588,21 @@ typedef union { x86_reg_emit ((inst), (dreg), (reg)); \ } while (0) +/** + * @x86_alu_reg8_reg8: + * Supports ALU operations between two 8-bit registers. + * dreg := dreg opc reg + * X86_Reg_No enum is used to specify the registers. + * Additionally is_*_h flags are used to specify what part + * of a given 32-bit register is used - high (TRUE) or low (FALSE). + * For example: dreg = X86_EAX, is_dreg_h = TRUE -> use AH + */ +#define x86_alu_reg8_reg8(inst,opc,dreg,reg,is_dreg_h,is_reg_h) \ + do { \ + *(inst)++ = (((unsigned char)(opc)) << 3) + 2; \ + x86_reg8_emit ((inst), (dreg), (reg), (is_dreg_h), (is_reg_h)); \ + } while (0) + #define x86_alu_reg_mem(inst,opc,reg,mem) \ do { \ *(inst)++ = (((unsigned char)(opc)) << 3) + 3; \ @@ -920,6 +1030,7 @@ typedef union { #define x86_widen_reg(inst,dreg,reg,is_signed,is_half) \ do { \ unsigned char op = 0xb6; \ + g_assert (is_half || X86_IS_BYTE_REG (reg)); \ *(inst)++ = (unsigned char)0x0f; \ if ((is_signed)) op += 0x08; \ if ((is_half)) op += 0x01; \ @@ -985,6 +1096,19 @@ typedef union { *(inst)++ = (unsigned char)0xc0+(map[(opc)]<<3)+((index)&0x07); \ } while (0) +/** + * @x86_fp_int_op_membase + * Supports FPU operations between ST(0) and integer operand in memory. + * Operation encoded using X86_FP_Opcode enum. + * Operand is addressed by [basereg + disp]. + * is_int specifies whether operand is int32 (TRUE) or int16 (FALSE). + */ +#define x86_fp_int_op_membase(inst,opc,basereg,disp,is_int) \ + do { \ + *(inst)++ = (is_int) ? (unsigned char)0xda : (unsigned char)0xde; \ + x86_membase_emit ((inst), opc, (basereg), (disp)); \ + } while (0) + #define x86_fstp(inst,index) \ do { \ *(inst)++ = (unsigned char)0xdd; \ @@ -1139,6 +1263,12 @@ typedef union { *(inst)++ = (unsigned char)0xe8; \ } while (0) +#define x86_fldpi(inst) \ + do { \ + *(inst)++ = (unsigned char)0xd9; \ + *(inst)++ = (unsigned char)0xeb; \ + } while (0) + #define x86_fst(inst,mem,is_double,pop_stack) \ do { \ *(inst)++ = (is_double) ? (unsigned char)0xdd: (unsigned char)0xd9; \ @@ -1187,6 +1317,31 @@ typedef union { } \ } while (0) +#define x86_fstsw(inst) \ + do { \ + *(inst)++ = (unsigned char)0x9b; \ + *(inst)++ = (unsigned char)0xdf; \ + *(inst)++ = (unsigned char)0xe0; \ + } while (0) + +/** + * @x86_fist_membase + * Converts content of ST(0) to integer and stores it at memory location + * addressed by [basereg + disp]. + * is_int specifies whether destination is int32 (TRUE) or int16 (FALSE). + */ +#define x86_fist_membase(inst,basereg,disp,is_int) \ + do { \ + if ((is_int)) { \ + *(inst)++ = (unsigned char)0xdb; \ + x86_membase_emit ((inst), 2, (basereg), (disp)); \ + } else { \ + *(inst)++ = (unsigned char)0xdf; \ + x86_membase_emit ((inst), 2, (basereg), (disp)); \ + } \ + } while (0) + + #define x86_push_reg(inst,reg) \ do { \ *(inst)++ = (unsigned char)0x50 + (reg); \ @@ -1216,10 +1371,18 @@ typedef union { x86_memindex_emit ((inst), 6, (basereg), (disp), (indexreg), (shift)); \ } while (0) +#define x86_push_imm_template(inst) x86_push_imm (inst, 0xf0f0f0f0) + #define x86_push_imm(inst,imm) \ do { \ - *(inst)++ = (unsigned char)0x68; \ - x86_imm_emit32 ((inst), (imm)); \ + int _imm = (int) (imm); \ + if (x86_is_imm8 (_imm)) { \ + *(inst)++ = (unsigned char)0x6A; \ + x86_imm_emit8 ((inst), (_imm)); \ + } else { \ + *(inst)++ = (unsigned char)0x68; \ + x86_imm_emit32 ((inst), (_imm)); \ + } \ } while (0) #define x86_pop_reg(inst,reg) \ @@ -1360,6 +1523,7 @@ typedef union { #define x86_set_reg(inst,cond,reg,is_signed) \ do { \ + g_assert (X86_IS_BYTE_REG (reg)); \ *(inst)++ = (unsigned char)0x0f; \ if ((is_signed)) \ *(inst)++ = x86_cc_signed_map [(cond)] + 0x20; \ @@ -1474,6 +1638,8 @@ typedef union { #define x86_fsin(inst) do { *(inst)++ = (unsigned char)0xd9; *(inst)++ = (unsigned char)0xfe; } while (0) #define x86_fcos(inst) do { *(inst)++ = (unsigned char)0xd9; *(inst)++ = (unsigned char)0xff; } while (0) #define x86_fabs(inst) do { *(inst)++ = (unsigned char)0xd9; *(inst)++ = (unsigned char)0xe1; } while (0) +#define x86_ftst(inst) do { *(inst)++ = (unsigned char)0xd9; *(inst)++ = (unsigned char)0xe4; } while (0) +#define x86_fxam(inst) do { *(inst)++ = (unsigned char)0xd9; *(inst)++ = (unsigned char)0xe5; } while (0) #define x86_fpatan(inst) do { *(inst)++ = (unsigned char)0xd9; *(inst)++ = (unsigned char)0xf3; } while (0) #define x86_fprem(inst) do { *(inst)++ = (unsigned char)0xd9; *(inst)++ = (unsigned char)0xf8; } while (0) #define x86_fprem1(inst) do { *(inst)++ = (unsigned char)0xd9; *(inst)++ = (unsigned char)0xf5; } while (0)