X-Git-Url: http://wien.tomnetworks.com/gitweb/?a=blobdiff_plain;f=hollywood.h;h=e957e99cc67c44dbaeeafe3f3b6a6209230d5abb;hb=6ecceb2e08b3503e8c500e01cd1ecdcb873dd3b0;hp=3f2dde48eb0ee7a0b0d0d6d3c9574882a29b78e0;hpb=0a6cd808a414dab189b1ffac82df6651dfb4ae34;p=ppcskel.git

diff --git a/hollywood.h b/hollywood.h
index 3f2dde4..e957e99 100644
--- a/hollywood.h
+++ b/hollywood.h
@@ -140,66 +140,39 @@ Copyright (C) 2008, 2009	John Kelley <wiidev@kelley.ca>
 #define		SDHC_REG_BASE		0xd070000
 
 /* OHCI0 Registers */
-
 #define 	OHCI0_REG_BASE 		0xd050000
 
-#define 	OHCI0_HC_REVISION 			(OHCI0_REG_BASE + 0x00)
-#define 	OHCI0_HC_CONTROL 			(OHCI0_REG_BASE + 0x04)
-#define 	OHCI0_HC_COMMAND_STATUS 	(OHCI0_REG_BASE + 0x08)
-#define 	OHCI0_HC_INT_STATUS 		(OHCI0_REG_BASE + 0x0C)
-
-#define 	OHCI0_HC_INT_ENABLE 		(OHCI0_REG_BASE + 0x10)
-#define 	OHCI0_HC_INT_DISABLE 		(OHCI0_REG_BASE + 0x14)
-#define 	OHCI0_HC_HCCA 				(OHCI0_REG_BASE + 0x18)
-#define 	OHCI0_HC_PERIOD_CURRENT_ED 	(OHCI0_REG_BASE + 0x1C)
-
-#define 	OHCI0_HC_CTRL_HEAD_ED 		(OHCI0_REG_BASE + 0x20)
-#define 	OHCI0_HC_CTRL_CURRENT_ED 	(OHCI0_REG_BASE + 0x24)
-#define 	OHCI0_HC_BULK_HEAD_ED 		(OHCI0_REG_BASE + 0x28)
-#define 	OHCI0_HC_BULK_CURRENT_ED 	(OHCI0_REG_BASE + 0x2C)
-
-#define 	OHCI0_HC_DONE_HEAD 		 	(OHCI0_REG_BASE + 0x30)
-#define 	OHCI0_HC_FM_INTERVAL 	 	(OHCI0_REG_BASE + 0x34)
-#define 	OHCI0_HC_FM_REMAINING 	 	(OHCI0_REG_BASE + 0x38)
-#define 	OHCI0_HC_FM_NUMBER 		 	(OHCI0_REG_BASE + 0x3C)
-
-#define 	OHCI0_HC_PERIODIC_START 	(OHCI0_REG_BASE + 0x40)
-#define 	OHCI0_HC_LS_THRESHOLD 	 	(OHCI0_REG_BASE + 0x44)
-#define 	OHCI0_HC_RH_DESCRIPTOR_A	(OHCI0_REG_BASE + 0x48)
-#define 	OHCI0_HC_RH_DESCRIPTOR_B  	(OHCI0_REG_BASE + 0x4C)
-
-#define 	OHCI0_HC_RH_STATUS 		 	(OHCI0_REG_BASE + 0x50)
-
 /* OHCI1 Registers */
-
 #define 	OHCI1_REG_BASE 		0xd060000
 
-#define 	OHCI1_HC_REVISION 			(OHCI1_REG_BASE + 0x00)
-#define 	OHCI1_HC_CONTROL 			(OHCI1_REG_BASE + 0x04)
-#define 	OHCI1_HC_COMMAND_STATUS 	(OHCI1_REG_BASE + 0x08)
-#define 	OHCI1_HC_INT_STATUS 		(OHCI1_REG_BASE + 0x0C)
-
-#define 	OHCI1_HC_INT_ENABLE 		(OHCI1_REG_BASE + 0x10)
-#define 	OHCI1_HC_INT_DISABLE 		(OHCI1_REG_BASE + 0x14)
-#define 	OHCI1_HC_HCCA 				(OHCI1_REG_BASE + 0x18)
-#define 	OHCI1_HC_PERIOD_CURRENT_ED 	(OHCI1_REG_BASE + 0x1C)
-
-#define 	OHCI1_HC_CTRL_HEAD_ED 		(OHCI1_REG_BASE + 0x20)
-#define 	OHCI1_HC_CTRL_CURRENT_ED 	(OHCI1_REG_BASE + 0x24)
-#define 	OHCI1_HC_BULK_HEAD_ED 		(OHCI1_REG_BASE + 0x28)
-#define 	OHCI1_HC_BULK_CURRENT_ED 	(OHCI1_REG_BASE + 0x2C)
-
-#define 	OHCI1_HC_DONE_HEAD 		 	(OHCI1_REG_BASE + 0x30)
-#define 	OHCI1_HC_FM_INTERVAL 	 	(OHCI1_REG_BASE + 0x34)
-#define 	OHCI1_HC_FM_REMAINING 	 	(OHCI1_REG_BASE + 0x38)
-#define 	OHCI1_HC_FM_NUMBER 		 	(OHCI1_REG_BASE + 0x3C)
-
-#define 	OHCI1_HC_PERIODIC_START 	(OHCI1_REG_BASE + 0x40)
-#define 	OHCI1_HC_LS_THRESHOLD 	 	(OHCI1_REG_BASE + 0x44)
-#define 	OHCI1_HC_RH_DESCRIPTOR_A	(OHCI1_REG_BASE + 0x48)
-#define 	OHCI1_HC_RH_DESCRIPTOR_B  	(OHCI1_REG_BASE + 0x4C)
-
-#define 	OHCI1_HC_RH_STATUS 		 	(OHCI1_REG_BASE + 0x50)
+#define 	OHCI_HC_REVISION 			0x00
+#define 	OHCI_HC_CONTROL 			0x04
+#define 	OHCI_HC_COMMAND_STATUS 		0x08
+#define 	OHCI_HC_INT_STATUS 			0x0C
+
+#define 	OHCI_HC_INT_ENABLE 			0x10
+#define 	OHCI_HC_INT_DISABLE 		0x14
+#define 	OHCI_HC_HCCA 				0x18
+#define 	OHCI_HC_PERIOD_CURRENT_ED 	0x1C
+
+#define 	OHCI_HC_CTRL_HEAD_ED 		0x20
+#define 	OHCI_HC_CTRL_CURRENT_ED 	0x24
+#define 	OHCI_HC_BULK_HEAD_ED 		0x28
+#define 	OHCI_HC_BULK_CURRENT_ED 	0x2C
+
+#define 	OHCI_HC_DONE_HEAD 		 	0x30
+#define 	OHCI_HC_FM_INTERVAL 	 	0x34
+#define 	OHCI_HC_FM_REMAINING 	 	0x38
+#define 	OHCI_HC_FM_NUMBER 		 	0x3C
+
+#define 	OHCI_HC_PERIODIC_START 		0x40
+#define 	OHCI_HC_LS_THRESHOLD 	 	0x44
+#define 	OHCI_HC_RH_DESCRIPTOR_A		0x48
+#define 	OHCI_HC_RH_DESCRIPTOR_B  	0x4C
+
+#define 	OHCI_HC_RH_STATUS 		 	0x50
+#define 	OHCI_HC_RH_PORT_STATUS_1 	0x54
+#define 	OHCI_HC_RH_PORT_STATUS_2 	0x58
 
 /* EHCI Registers */
 #define 	EHCI_REG_BASE 		0xd040000