X-Git-Url: http://wien.tomnetworks.com/gitweb/?a=blobdiff_plain;f=dt%2Fdt.qsf;fp=dt%2Fdt.qsf;h=a9102b02dd2aa7a1a62ce2916547b292a1ce5c2b;hb=e42af2345f9574b9c54ac4deb799670581c8680d;hp=1a461c3c0af95d206ecd4ba536d1f1b25f5218a4;hpb=98556b5c34ae0c1c5067453a5b923dfd1c5ce5c6;p=calu.git

diff --git a/dt/dt.qsf b/dt/dt.qsf
index 1a461c3..a9102b0 100644
--- a/dt/dt.qsf
+++ b/dt/dt.qsf
@@ -59,6 +59,27 @@ set_location_assignment PIN_178 -to bus_tx
 set_location_assignment PIN_152 -to sys_clk
 set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "AS INPUT TRI-STATED"
 
+
+set_global_assignment -name SMART_RECOMPILE ON
+set_global_assignment -name ENABLE_DRC_SETTINGS ON
+set_global_assignment -name ENABLE_CLOCK_LATENCY ON
+set_global_assignment -name ENABLE_RECOVERY_REMOVAL_ANALYSIS ON
+set_global_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE SPEED
+set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON
+set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON
+set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING ON
+set_global_assignment -name ROUTER_LCELL_INSERTION_AND_LOGIC_DUPLICATION ON
+set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL MAXIMUM
+set_global_assignment -name AUTO_PACKED_REGISTERS_CYCLONE NORMAL
+set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
+set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP ON
+set_global_assignment -name MUX_RESTRUCTURE OFF
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS"
+set_location_assignment PIN_153 -to bus_rx
+set_location_assignment PIN_42 -to sys_res_unsync
+set_global_assignment -name FMAX_REQUIREMENT "50 MHz"
+set_global_assignment -name VHDL_FILE ../cpu/src/r_w_ram_be_b.vhd
+set_global_assignment -name VHDL_FILE ../cpu/src/r_w_ram_be.vhd
 set_global_assignment -name VHDL_FILE ../cpu/src/rom.vhd
 set_global_assignment -name VHDL_FILE ../cpu/src/rom_b.vhd
 set_global_assignment -name VHDL_FILE ../cpu/src/extension_7seg_pkg.vhd
@@ -104,22 +125,4 @@ set_global_assignment -name VHDL_FILE ../cpu/src/exec_op/shift_op_b.vhd
 set_global_assignment -name VHDL_FILE ../cpu/src/exec_op/or_op_b.vhd
 set_global_assignment -name VHDL_FILE ../cpu/src/exec_op/and_op_b.vhd
 set_global_assignment -name VHDL_FILE ../cpu/src/exec_op/add_op_b.vhd
-
-set_global_assignment -name SMART_RECOMPILE ON
-set_global_assignment -name ENABLE_DRC_SETTINGS ON
-set_global_assignment -name ENABLE_CLOCK_LATENCY ON
-set_global_assignment -name ENABLE_RECOVERY_REMOVAL_ANALYSIS ON
-set_global_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE SPEED
-set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON
-set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON
-set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING ON
-set_global_assignment -name ROUTER_LCELL_INSERTION_AND_LOGIC_DUPLICATION ON
-set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL MAXIMUM
-set_global_assignment -name AUTO_PACKED_REGISTERS_CYCLONE NORMAL
-set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
-set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP ON
-set_global_assignment -name MUX_RESTRUCTURE OFF
-set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS"
-set_location_assignment PIN_153 -to bus_rx
-set_location_assignment PIN_42 -to sys_res_unsync
 set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
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