X-Git-Url: http://wien.tomnetworks.com/gitweb/?a=blobdiff_plain;f=demo%2Fquartus%2Fdemo.flow.rpt;fp=demo%2Fquartus%2Fdemo.flow.rpt;h=69565cb77b17f80ddc53bf4ce9fa5e70fbcaf120;hb=e42195f0e9941cd25a1b04248c39c799e44d83f3;hp=0000000000000000000000000000000000000000;hpb=35f136212f77eb77098373ded0efdd9bad932163;p=hwmod.git diff --git a/demo/quartus/demo.flow.rpt b/demo/quartus/demo.flow.rpt new file mode 100644 index 0000000..69565cb --- /dev/null +++ b/demo/quartus/demo.flow.rpt @@ -0,0 +1,112 @@ +Flow report for demo +Mon Mar 30 19:53:36 2009 +Quartus II Version 7.0 Build 33 02/05/2007 SJ Full Version + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Flow Summary + 3. Flow Settings + 4. Flow Non-Default Global Settings + 5. Flow Elapsed Time + 6. Flow Log + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 1991-2007 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. + + + ++------------------------------------------------------------------------------+ +; Flow Summary ; ++------------------------------------+-----------------------------------------+ +; Flow Status ; Successful - Mon Mar 30 19:53:36 2009 ; +; Quartus II Version ; 7.0 Build 33 02/05/2007 SJ Full Version ; +; Revision Name ; demo ; +; Top-level Entity Name ; demo_top ; +; Family ; Cyclone II ; +; Device ; EP2C35F484C6 ; +; Timing Models ; Final ; +; Met timing requirements ; Yes ; +; Total logic elements ; 65 / 33,216 ( < 1 % ) ; +; Total combinational functions ; 65 / 33,216 ( < 1 % ) ; +; Dedicated logic registers ; 16 / 33,216 ( < 1 % ) ; +; Total registers ; 16 ; +; Total pins ; 10 / 322 ( 3 % ) ; +; Total virtual pins ; 0 ; +; Total memory bits ; 0 / 483,840 ( 0 % ) ; +; Embedded Multiplier 9-bit elements ; 0 / 70 ( 0 % ) ; +; Total PLLs ; 1 / 4 ( 25 % ) ; ++------------------------------------+-----------------------------------------+ + + ++-----------------------------------------+ +; Flow Settings ; ++-------------------+---------------------+ +; Option ; Setting ; ++-------------------+---------------------+ +; Start date & time ; 03/30/2009 19:52:35 ; +; Main task ; Compilation ; +; Revision Name ; demo ; ++-------------------+---------------------+ + + ++-------------------------------------------------------------------------------------------------------------------+ +; Flow Non-Default Global Settings ; ++--------------------------------------------+-----------------------+---------------+-------------+----------------+ +; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ; ++--------------------------------------------+-----------------------+---------------+-------------+----------------+ +; EDA_INCLUDE_VHDL_CONFIGURATION_DECLARATION ; On ; -- ; -- ; eda_simulation ; +; EDA_OUTPUT_DATA_FORMAT ; Vhdl ; -- ; -- ; eda_simulation ; +; EDA_SIMULATION_RUN_SCRIPT ; ../sim/demo_tb_rtl.do ; -- ; -- ; eda_simulation ; +; EDA_SIMULATION_TOOL ; ModelSim (VHDL) ; ; -- ; -- ; +; EDA_TEST_BENCH_ENABLE_STATUS ; NOT_USED ; -- ; -- ; eda_simulation ; +; PARTITION_NETLIST_TYPE ; SOURCE ; -- ; demo_top ; Top ; +; TOP_LEVEL_ENTITY ; demo_top ; demo ; -- ; -- ; ++--------------------------------------------+-----------------------+---------------+-------------+----------------+ + + ++----------------------------------------+ +; Flow Elapsed Time ; ++-------------------------+--------------+ +; Module Name ; Elapsed Time ; ++-------------------------+--------------+ +; Analysis & Synthesis ; 00:00:03 ; +; Partition Merge ; 00:00:01 ; +; Fitter ; 00:00:14 ; +; Assembler ; 00:00:27 ; +; Classic Timing Analyzer ; 00:00:01 ; +; EDA Netlist Writer ; 00:00:01 ; +; Total ; 00:00:47 ; ++-------------------------+--------------+ + + +------------ +; Flow Log ; +------------ +quartus_map --read_settings_files=on --write_settings_files=off demo -c demo +quartus_cdb --read_settings_files=off --write_settings_files=off demo -c demo --merge=on +quartus_fit --read_settings_files=off --write_settings_files=off demo -c demo +quartus_asm --read_settings_files=off --write_settings_files=off demo -c demo +quartus_tan --read_settings_files=off --write_settings_files=off demo -c demo --timing_analysis_only +quartus_eda --read_settings_files=off --write_settings_files=off demo -c demo + + +