X-Git-Url: http://wien.tomnetworks.com/gitweb/?a=blobdiff_plain;f=cpu%2Fsrc%2Fwriteback_stage_b.vhd;h=a031207123e2836ec47551455ac1df7391623ae4;hb=e10c1f8d87053aadfbd9d8ff1abb2219debe16d5;hp=a64906b8f96cd936f6f95a03548918ab9926458f;hpb=e42af2345f9574b9c54ac4deb799670581c8680d;p=calu.git

diff --git a/cpu/src/writeback_stage_b.vhd b/cpu/src/writeback_stage_b.vhd
index a64906b..a031207 100755
--- a/cpu/src/writeback_stage_b.vhd
+++ b/cpu/src/writeback_stage_b.vhd
@@ -9,6 +9,7 @@ use work.mem_pkg.all;
 use work.extension_pkg.all;
 use work.extension_uart_pkg.all;
 use work.extension_7seg_pkg.all;
+use work.extension_imp_pkg.all;
 
 architecture behav of writeback_stage is
 
@@ -17,8 +18,12 @@ signal data_addr : word_t;
 
 signal wb_reg, wb_reg_nxt : writeback_rec;
 
-signal ext_uart,ext_timer,ext_gpmp,ext_7seg :  extmod_rec;
-signal ext_uart_out, ext_timer_out, ext_gpmp_out : gp_register_t;
+signal ext_uart,ext_timer,ext_gpmp,ext_7seg,ext_int,ext_imp :  extmod_rec;
+signal ext_uart_out, ext_timer_out, ext_gpmp_out, ext_int_out,ext_imp_out : gp_register_t;
+
+--signal int_req : interrupt_t;
+signal uart_int : std_logic;
+
 
 signal sel_nxt, dmem_we, ext_anysel : std_logic;
 
@@ -29,6 +34,23 @@ begin
 	ext_timer_out <= (others => '0'); --TODO: delete when timer is connected
 	ext_gpmp_out <= (others => '0'); --TODO: delete when gpm is connected
 
+	spartan3e: if FPGATYPE = "s3e" generate
+		data_ram : ram_xilinx
+		generic map (
+			DATA_ADDR_WIDTH
+		)
+		port map (
+			clk,
+			data_addr(DATA_ADDR_WIDTH+1 downto 2),
+			data_addr(DATA_ADDR_WIDTH+1 downto 2),
+			wb_reg_nxt.byte_en,
+			dmem_we,
+			wb_reg_nxt.data, --ram_data,
+			data_ram_read
+		);
+	end generate;
+	-- else generate gibt es erst mit vhdl 2008 ...
+	altera: if FPGATYPE /= "s3e" generate
 	data_ram : r_w_ram_be
 		generic map (
 			DATA_ADDR_WIDTH
@@ -43,6 +65,7 @@ begin
 			wb_reg_nxt.data, --ram_data,
 			data_ram_read
 		);
+	end generate;
 
 uart : extension_uart 
 	generic	map(
@@ -53,10 +76,26 @@ uart : extension_uart
 			reset,
 			ext_uart,
 			ext_uart_out,
+			uart_int,
 			bus_rx,
 			bus_tx
 		);
 	
+imp : extension_imp 
+	generic	map(
+		RESET_VALUE
+		)
+	port map(
+			clk ,
+			reset,
+			ext_imp,
+			ext_imp_out,
+			im_addr,
+			im_data,
+			new_im_data_out
+		);
+	
+	altera_7seg: if FPGATYPE /= "s3e" generate
 sseg : extension_7seg
 	generic map(
 		RESET_VALUE
@@ -70,6 +109,23 @@ sseg : extension_7seg
 		sseg2,
 		sseg3
 		);
+	end generate;
+
+interrupt : extension_interrupt
+	generic map(
+		RESET_VALUE
+		)
+	port map(
+		clk,
+		reset,
+		ext_int,
+		ext_int_out,
+
+		uart_int,
+
+		int_req
+
+		);
 	
 syn: process(clk, reset)
 
@@ -282,31 +338,73 @@ begin
   ext_7seg.sel <='0';
   ext_timer.sel <='0';
   ext_gpmp.sel <='0';
+  ext_int.sel <= '0';
+  ext_imp.sel <= '0';
   
   ext_uart.wr_en <= wr_en;
   ext_7seg.wr_en <= wr_en;
   ext_timer.wr_en <= wr_en;
   ext_gpmp.wr_en <= wr_en;
-  
+  ext_int.wr_en <= wr_en;  
+  ext_imp.wr_en <= wr_en;  
+
   ext_uart.byte_en <= byte_en;
   ext_7seg.byte_en <= byte_en;
   ext_timer.byte_en <= byte_en;
   ext_gpmp.byte_en <= byte_en;
-  
+  ext_int.byte_en <= byte_en;  
+  ext_imp.byte_en <= byte_en; 
+
   ext_uart.addr <= addr;
   ext_7seg.addr <= addr;
   ext_timer.addr <= addr;
   ext_gpmp.addr <= addr;
+  ext_int.addr <= addr;
+  ext_imp.addr <= addr;
 
   ext_uart.data <= data;
   ext_7seg.data <= data;
   ext_timer.data <= data;
   ext_gpmp.data <= data;
+  ext_int.data <= data;
+  ext_imp.data <= data;
+
    -- wenn ich hier statt dem 4rer die konstante nehme dann gibts an fehler wegen nicht lokaler variable -.-
  case addrid is
     when EXT_UART_ADDR => 
     	ext_uart.sel <= enable;
-		ext_anysel <= enable;
+	ext_anysel <= enable;
+
+--		ext_uart.wr_en <= wb_reg_nxt.dmem_write_en;
+--  		ext_uart.data <= ram_data;
+--		ext_uart.addr <= wb_reg_nxt.address(31 downto 2);
+--		case wb_reg_nxt.address(1 downto 0) is
+--				when "00" => ext_uart.byte_en <= "0001";
+--				when "01" => ext_uart.byte_en <= "0010";
+--				when "10" => ext_uart.byte_en <= "0100";
+--				--when "11" => ext_uart.byte_en <= "1000";
+--				when "11" => ext_uart.byte_en <= "1111";
+--				when others => null;
+--			end case;
+    when EXT_IMP_ADDR => 
+    	ext_imp.sel <= enable;
+	ext_anysel <= enable;
+
+--		ext_uart.wr_en <= wb_reg_nxt.dmem_write_en;
+--  		ext_uart.data <= ram_data;
+--		ext_uart.addr <= wb_reg_nxt.address(31 downto 2);
+--		case wb_reg_nxt.address(1 downto 0) is
+--				when "00" => ext_uart.byte_en <= "0001";
+--				when "01" => ext_uart.byte_en <= "0010";
+--				when "10" => ext_uart.byte_en <= "0100";
+--				--when "11" => ext_uart.byte_en <= "1000";
+--				when "11" => ext_uart.byte_en <= "1111";
+--				when others => null;
+--			end case;
+
+    when EXT_INT_ADDR => 
+    	ext_int.sel <= enable;
+	ext_anysel <= enable;
 
 --		ext_uart.wr_en <= wb_reg_nxt.dmem_write_en;
 --  		ext_uart.data <= ram_data;