X-Git-Url: http://wien.tomnetworks.com/gitweb/?a=blobdiff_plain;f=cpu%2Fsrc%2Fwriteback_stage_b.vhd;h=6d03873d9dff12c22bf05af03b823dedc84409da;hb=d4a0ea68530da911bc41c44b24d244c7dc198190;hp=acf0f7db2032a88263d11df7b924e9aeac5450a5;hpb=0b3367ce6428a2e3e553fae6a7098b6f9d2ab93f;p=calu.git

diff --git a/cpu/src/writeback_stage_b.vhd b/cpu/src/writeback_stage_b.vhd
index acf0f7d..6d03873 100755
--- a/cpu/src/writeback_stage_b.vhd
+++ b/cpu/src/writeback_stage_b.vhd
@@ -95,6 +95,8 @@ imp : extension_imp
 			new_im_data_out
 		);
 	
+	rem7seg: if "a" /= "a" generate
+
 	altera_7seg: if FPGATYPE /= "s3e" generate
 sseg : extension_7seg
 	generic map(
@@ -103,13 +105,15 @@ sseg : extension_7seg
 	port map(
 		clk,
 		reset,
-		ext_7seg,
-		sseg0,
-		sseg1,
-		sseg2,
-		sseg3
+		--ext_7seg,
+		ext_7seg
+		--sseg0,
+		--sseg1,
+		--sseg2,
+		--sseg3
 		);
 	end generate;
+	end generate;
 
 interrupt : extension_interrupt
 	generic map(
@@ -234,7 +238,7 @@ begin
 	if (alu_jmp = '1' and wb_reg.dmem_en = '1' and wb_reg.dmem_write_en = '0' and write_en = '0') then
 		jump_addr <= data_ram_read;
 	else
-		jump_addr <= result;	
+		jump_addr <= result;
 	end if;
 
 --	if alu_jmp = '0' and br_pred = '1' and write_en = '0' then
@@ -269,10 +273,10 @@ begin
 	data_addr <= (others => '0');
 	dmem_we <= '0';
 	
-	if (wb_reg.address(DATA_ADDR_WIDTH+2) /= '1') then
+	if (wb_reg.address(DATA_ADDR_WIDTH+3) /= '1') then
 		data_out := data_ram_read;
 	else
-		reg_we_v := reg_we_v and ext_anysel;
+		reg_we_v := reg_we_v and (ext_anysel or not(wb_reg.dmem_en));
 		data_out := data_ram_read_ext;
 	end if;
 	
@@ -306,7 +310,7 @@ begin
 	
 	data_out := to_stdlogicvector(to_bitvector(data_out) srl to_integer(unsigned(wb_reg.address(BYTEADDR-1 downto 0)))*byte_t'length); 
 	
-	if (wb_reg_nxt.address(DATA_ADDR_WIDTH+2) /= '1') then
+	if (wb_reg_nxt.address(DATA_ADDR_WIDTH+3) /= '1') then
 		data_addr(DATA_ADDR_WIDTH+1 downto 0) <= wb_reg_nxt.address(DATA_ADDR_WIDTH+1 downto 0);
 		dmem_we <= wb_reg_nxt.dmem_write_en;
 	end if;