X-Git-Url: http://wien.tomnetworks.com/gitweb/?a=blobdiff_plain;f=cpu%2Fsrc%2Fwriteback_stage_b.vhd;h=6a3a4e6c0e11ef5b500e29f9ba24e5ed698d9c40;hb=0ba0c7effbaf554ad42db51334581859a0570bfa;hp=1a59b1e79117057d1a5d6e5bbbb56e9bdd50375e;hpb=ce413b7c5c11c0d2ffda62afbe8a84bbbb7c9d5f;p=calu.git diff --git a/cpu/src/writeback_stage_b.vhd b/cpu/src/writeback_stage_b.vhd index 1a59b1e..6a3a4e6 100755 --- a/cpu/src/writeback_stage_b.vhd +++ b/cpu/src/writeback_stage_b.vhd @@ -9,6 +9,8 @@ use work.mem_pkg.all; use work.extension_pkg.all; use work.extension_uart_pkg.all; use work.extension_7seg_pkg.all; +use work.extension_imp_pkg.all; +use work.extension_timer_pkg.all; architecture behav of writeback_stage is @@ -17,46 +19,83 @@ signal data_addr : word_t; signal wb_reg, wb_reg_nxt : writeback_rec; -signal ext_uart,ext_timer,ext_gpmp,ext_7seg : extmod_rec; -signal ext_uart_out, ext_timer_out, ext_gpmp_out : gp_register_t; +signal ext_uart,ext_timer,ext_gpmp,ext_7seg,ext_int,ext_imp : extmod_rec; +signal ext_uart_out, ext_timer_out, ext_gpmp_out, ext_int_out,ext_imp_out : gp_register_t; -signal sel_nxt, dmem_we, bus_rx, ext_anysel : std_logic; +--signal int_req : interrupt_t; +signal uart_int : std_logic; + + +signal sel_nxt, dmem_we, ext_anysel : std_logic; signal calc_mem_res : gp_register_t; begin - - ext_timer_out <= (others => '0'); --TODO: delete when timer is connected ext_gpmp_out <= (others => '0'); --TODO: delete when gpm is connected - data_ram : r_w_ram + spartan3e: if FPGATYPE = "s3e" generate + data_ram : ram_xilinx generic map ( - DATA_ADDR_WIDTH, - WORD_WIDTH + DATA_ADDR_WIDTH + ) + port map ( + clk, + data_addr(DATA_ADDR_WIDTH+1 downto 2), + data_addr(DATA_ADDR_WIDTH+1 downto 2), + wb_reg_nxt.byte_en, + dmem_we, + wb_reg_nxt.data, --ram_data, + data_ram_read + ); + end generate; + -- else generate gibt es erst mit vhdl 2008 ... + altera: if FPGATYPE /= "s3e" generate + data_ram : r_w_ram_be + generic map ( + DATA_ADDR_WIDTH ) port map ( clk, data_addr(DATA_ADDR_WIDTH+1 downto 2), data_addr(DATA_ADDR_WIDTH+1 downto 2), + wb_reg_nxt.byte_en, dmem_we, - ram_data, + wb_reg_nxt.data, --ram_data, data_ram_read ); + end generate; uart : extension_uart generic map( - RESET_VALUE + RESET_VALUE, + CLK_BAUD ) port map( clk , reset, ext_uart, ext_uart_out, + uart_int, bus_rx, bus_tx ); +imp : extension_imp + generic map( + RESET_VALUE + ) + port map( + clk , + reset, + ext_imp, + ext_imp_out, + im_addr, + im_data, + new_im_data_out + ); + + altera_7seg: if FPGATYPE /= "s3e" generate sseg : extension_7seg generic map( RESET_VALUE @@ -70,6 +109,27 @@ sseg : extension_7seg sseg2, sseg3 ); + end generate; + +interrupt : extension_interrupt + generic map( + RESET_VALUE + ) + port map( + clk, + reset, + ext_int, + ext_int_out, + + uart_int, + + int_req + + ); + +timer : extension_timer + generic map(RESET_VALUE) + port map(clk, reset, ext_timer, ext_timer_out); syn: process(clk, reset) @@ -81,13 +141,11 @@ begin wb_reg.dmem_write_en <= '0'; wb_reg.hword <= '0'; wb_reg.byte_s <= '0'; - bus_rx <= '1'; wb_reg.byte_en <= (others => '0'); wb_reg.data <= (others =>'0'); elsif rising_edge(clk) then wb_reg <= wb_reg_nxt; - bus_rx <= '1'; end if; end process; @@ -103,6 +161,7 @@ end process; shift_input: process(data_ram_read, address, dmem_en, dmem_write_en, hword, wb_reg, result, byte_s, alu_jmp, br_pred, write_en, ram_data) variable byte_en : byte_en_t; +variable address_val : std_logic_vector(1 downto 0); begin wb_reg_nxt.address <= address; wb_reg_nxt.dmem_en <= dmem_en; @@ -114,19 +173,31 @@ begin wb_reg_nxt.data <= ram_data; byte_en := (others => '0'); + address_val := address(BYTEADDR-1 downto 0); if dmem_en = '1' then if hword = '1' then - case address(BYTEADDR-1 downto 0) is - when "00" => byte_en(1 downto 0) := "11"; - when "10" => byte_en(3 downto 2) := "11"; +-- case address(BYTEADDR-1 downto 0) is + case address_val is + when "00" => + byte_en(1 downto 0) := "11"; + when "10" => + byte_en(3 downto 2) := "11"; + wb_reg_nxt.data(31 downto 16) <= ram_data(15 downto 0); when others => null; end case; elsif byte_s = '1' then - case address(BYTEADDR-1 downto 0) is +-- case address(BYTEADDR-1 downto 0) is + case address_val is when "00" => byte_en(0) := '1'; - when "01" => byte_en(1) := '1'; - when "10" => byte_en(2) := '1'; - when "11" => byte_en(3) := '1'; + when "01" => + byte_en(1) := '1'; + wb_reg_nxt.data(15 downto 8) <= ram_data(7 downto 0); + when "10" => + byte_en(2) := '1'; + wb_reg_nxt.data(23 downto 16) <= ram_data(7 downto 0); + when "11" => + byte_en(3) := '1'; + wb_reg_nxt.data(31 downto 24) <= ram_data(7 downto 0); when others => null; end case; else @@ -163,7 +234,7 @@ begin if (alu_jmp = '1' and wb_reg.dmem_en = '1' and wb_reg.dmem_write_en = '0' and write_en = '0') then jump_addr <= data_ram_read; else - jump_addr <= result; + jump_addr <= result; end if; -- if alu_jmp = '0' and br_pred = '1' and write_en = '0' then @@ -188,7 +259,7 @@ end process; -out_logic: process(write_en, result_addr, wb_reg, alu_jmp, wb_reg_nxt, data_ram_read_ext, calc_mem_res, data_ram_read, ext_anysel) +out_logic: process(write_en, result_addr, wb_reg, alu_jmp, wb_reg_nxt, data_ram_read_ext, calc_mem_res, data_ram_read, ext_anysel, result, hword, byte_s) variable reg_we_v : std_logic; variable data_out : gp_register_t; begin @@ -198,7 +269,7 @@ begin data_addr <= (others => '0'); dmem_we <= '0'; - if (wb_reg.address(DATA_ADDR_WIDTH+2) /= '1') then + if (wb_reg.address(DATA_ADDR_WIDTH+3) /= '1') then data_out := data_ram_read; else reg_we_v := reg_we_v and ext_anysel; @@ -218,15 +289,34 @@ begin data_out(4*byte_t'length-1 downto 3*byte_t'length) := (others => '0'); end if; - data_out := to_stdlogicvector(to_bitvector(data_out) srl to_integer(unsigned(wb_reg.address(BYTEADDR-1 downto 0)))); - if (wb_reg_nxt.address(DATA_ADDR_WIDTH+2) /= '1') then +-- if wb_reg.hword = '1' or wb_reg.byte_s = '1' then +-- if wb_reg.address(1)='1' then +-- data_out(hword_t'range) := data_out(data_out'high downto (data_out'length/2)); +-- end if; +-- data_out(data_out'high downto (data_out'length/2)) := (others => '0'); +-- if byte_s = '1' then +-- if wb_reg.address(0) = '1' then +-- data_out(byte_t'range) := data_out(hword_t'high downto (hword_t'length/2)); +-- end if; +-- data_out(hword_t'high downto (hword_t'length/2)) := (others => '0'); +-- end if; +-- end if; + + + data_out := to_stdlogicvector(to_bitvector(data_out) srl to_integer(unsigned(wb_reg.address(BYTEADDR-1 downto 0)))*byte_t'length); + + if (wb_reg_nxt.address(DATA_ADDR_WIDTH+3) /= '1') then data_addr(DATA_ADDR_WIDTH+1 downto 0) <= wb_reg_nxt.address(DATA_ADDR_WIDTH+1 downto 0); dmem_we <= wb_reg_nxt.dmem_write_en; end if; regfile_val <= data_out; + if wb_reg.dmem_en = '0' then + regfile_val <= result; + end if; + reg_we <= reg_we_v; end process; @@ -236,7 +326,7 @@ addr_de_mult: process(wb_reg, wb_reg_nxt, ram_data, sel_nxt, ext_uart_out, ext_g variable wr_en, enable : std_logic; -- these are all registered variable byte_en : byte_en_t; -- if a module needs the nxt signals it has to manually select them variable addr : ext_addr_t; -- for example the data memory, because it already has input registers -variable addrid : ext_addrid_t; +variable addrid : std_logic_vector(27 downto 0);--ext_addrid_t; variable data : gp_register_t; begin @@ -252,31 +342,74 @@ begin ext_7seg.sel <='0'; ext_timer.sel <='0'; ext_gpmp.sel <='0'; + ext_int.sel <= '0'; + ext_imp.sel <= '0'; ext_uart.wr_en <= wr_en; ext_7seg.wr_en <= wr_en; ext_timer.wr_en <= wr_en; ext_gpmp.wr_en <= wr_en; - + ext_int.wr_en <= wr_en; + ext_imp.wr_en <= wr_en; + ext_uart.byte_en <= byte_en; ext_7seg.byte_en <= byte_en; ext_timer.byte_en <= byte_en; ext_gpmp.byte_en <= byte_en; - + ext_int.byte_en <= byte_en; + ext_imp.byte_en <= byte_en; + ext_uart.addr <= addr; ext_7seg.addr <= addr; ext_timer.addr <= addr; ext_gpmp.addr <= addr; + ext_int.addr <= addr; + ext_imp.addr <= addr; ext_uart.data <= data; ext_7seg.data <= data; ext_timer.data <= data; ext_gpmp.data <= data; + ext_int.data <= data; + ext_imp.data <= data; + -- wenn ich hier statt dem 4rer die konstante nehme dann gibts an fehler wegen nicht lokaler variable -.- case addrid is when EXT_UART_ADDR => ext_uart.sel <= enable; - ext_anysel <= enable; + ext_anysel <= enable; + +-- ext_uart.wr_en <= wb_reg_nxt.dmem_write_en; +-- ext_uart.data <= ram_data; +-- ext_uart.addr <= wb_reg_nxt.address(31 downto 2); +-- case wb_reg_nxt.address(1 downto 0) is +-- when "00" => ext_uart.byte_en <= "0001"; +-- when "01" => ext_uart.byte_en <= "0010"; +-- when "10" => ext_uart.byte_en <= "0100"; +-- --when "11" => ext_uart.byte_en <= "1000"; +-- when "11" => ext_uart.byte_en <= "1111"; +-- when others => null; +-- end case; + when EXT_IMP_ADDR => + ext_imp.sel <= enable; + ext_anysel <= enable; + +-- ext_uart.wr_en <= wb_reg_nxt.dmem_write_en; +-- ext_uart.data <= ram_data; +-- ext_uart.addr <= wb_reg_nxt.address(31 downto 2); +-- case wb_reg_nxt.address(1 downto 0) is +-- when "00" => ext_uart.byte_en <= "0001"; +-- when "01" => ext_uart.byte_en <= "0010"; +-- when "10" => ext_uart.byte_en <= "0100"; +-- --when "11" => ext_uart.byte_en <= "1000"; +-- when "11" => ext_uart.byte_en <= "1111"; +-- when others => null; +-- end case; + + when EXT_INT_ADDR => + ext_int.sel <= enable; + ext_anysel <= enable; + -- ext_uart.wr_en <= wb_reg_nxt.dmem_write_en; -- ext_uart.data <= ram_data; -- ext_uart.addr <= wb_reg_nxt.address(31 downto 2); @@ -292,6 +425,7 @@ begin when EXT_7SEG_ADDR => ext_7seg.sel <= enable; ext_anysel <= enable; + -- ext_7seg.wr_en <= wb_regdmem_write_en; -- ext_7seg.data <= ram_data; -- ext_7seg.addr <= wb_reg_nxt.address(31 downto 2); @@ -319,9 +453,9 @@ begin -- when "11" => ext_timer.byte_en <= "1000"; -- when others => null; -- end case; - when EXT_GPMP_ADDR => - ext_gpmp.sel <= enable; - ext_anysel <= enable; +-- when EXT_GPMP_ADDR => + -- ext_gpmp.sel <= enable; +-- ext_anysel <= enable; -- ext_gpmp.wr_en <= wb_reg_nxt.dmem_write_en; -- ext_gpmp.data <= ram_data; -- ext_gpmp.addr <= wb_reg_nxt.address(wb_reg_nxt.address'high downto BYTEADDR);