X-Git-Url: http://wien.tomnetworks.com/gitweb/?a=blobdiff_plain;f=cpu%2Fsrc%2Fwriteback_stage.vhd;h=ff31450b4cf8b72ee491fa393e2509c44b4c9bc5;hb=a37bfd1075f405931099ba5cc347b3954855675e;hp=256fa55783fb168781b568c4a31da661958a7cae;hpb=51ceb8fbeead4e281090bffefd2d9f1757c23955;p=calu.git

diff --git a/cpu/src/writeback_stage.vhd b/cpu/src/writeback_stage.vhd
index 256fa55..ff31450 100644
--- a/cpu/src/writeback_stage.vhd
+++ b/cpu/src/writeback_stage.vhd
@@ -10,8 +10,9 @@ entity writeback_stage is
 			-- active reset value
 			RESET_VALUE : std_logic;
 			-- active logic value
-			LOGIC_ACT : std_logic
-			
+			LOGIC_ACT : std_logic;
+			FPGATYPE : string;
+			CLK_BAUD : integer
 			);
 	port(
 		--System inputs
@@ -24,7 +25,7 @@ entity writeback_stage is
 			ram_data : in word_t;		--ureg
 			alu_jmp : in std_logic;		--reg
 			br_pred : in std_logic;		--reg
-			write_en : in std_logic;	--reg  (register file)
+			write_en : in std_logic;	--reg  (register file) bei jump 1 wenn addr in result
 			dmem_en : in std_logic;		--ureg (jump addr in mem or in address)
 			dmem_write_en : in std_logic;	--ureg
 			hword : in std_logic;		--ureg
@@ -34,7 +35,22 @@ entity writeback_stage is
 			reg_we : out std_logic;
 			reg_addr : out gp_addr_t;
 			jump_addr : out instruction_addr_t;
-			jump : out std_logic
+			jump : out std_logic;
+			-- hallo stefan mir adden da jetzt mal schnell an uart port :D
+			bus_tx : out std_logic;
+			bus_rx : in std_logic;
+			-- instruction memory program port :D
+			new_im_data_out : out std_logic;
+			im_addr : out gp_register_t;
+			im_data : out gp_register_t;
+			
+			--sseg0 : out std_logic_vector(0 to 6);
+			--sseg1 : out std_logic_vector(0 to 6);
+			--sseg2 : out std_logic_vector(0 to 6);
+			--sseg3 : out std_logic_vector(0 to 6);
+
+			int_req : out interrupt_t
+
 		);
 		
 end writeback_stage;