X-Git-Url: http://wien.tomnetworks.com/gitweb/?a=blobdiff_plain;f=cpu%2Fsrc%2Fwriteback_stage.vhd;h=aacba01de09a655846e40b1ba7b08d0b92ffbf10;hb=59b64378e94e8db6225a30c8d62e7472c66f675b;hp=d4d669c5d936f708e2ddf00b0c9fbb08800720d5;hpb=083ca8d3fad132e0c75fe34db350d4c789aff75f;p=calu.git

diff --git a/cpu/src/writeback_stage.vhd b/cpu/src/writeback_stage.vhd
index d4d669c..aacba01 100644
--- a/cpu/src/writeback_stage.vhd
+++ b/cpu/src/writeback_stage.vhd
@@ -38,6 +38,10 @@ entity writeback_stage is
 			-- hallo stefan mir adden da jetzt mal schnell an uart port :D
 			bus_tx : out std_logic;
 			bus_rx : in std_logic;
+			-- instruction memory program port :D
+			new_im_data_out : out std_logic;
+			im_addr : out gp_register_t;
+			im_data : out gp_register_t;
 			
 			sseg0 : out std_logic_vector(0 to 6);
 			sseg1 : out std_logic_vector(0 to 6);