X-Git-Url: http://wien.tomnetworks.com/gitweb/?a=blobdiff_plain;f=cpu%2Fsrc%2Fr_w_ram_b.vhd;h=f795dc1ca76aa2be70245618bd11098931ac2c56;hb=1968f329b10681b760faec9369aa893cd2af8d44;hp=45779da81a912c35414cb7517c0f4dbe3d5249df;hpb=9b61bb3513cd762f9714fb94ab434b4cbc616ea3;p=calu.git

diff --git a/cpu/src/r_w_ram_b.vhd b/cpu/src/r_w_ram_b.vhd
index 45779da..f795dc1 100644
--- a/cpu/src/r_w_ram_b.vhd
+++ b/cpu/src/r_w_ram_b.vhd
@@ -1,3 +1,24 @@
+--   `Deep Thought', a softcore CPU implemented on a FPGA
+--
+--  Copyright (C) 2010 Markus Hofstaetter <markus.manrow@gmx.at>
+--  Copyright (C) 2010 Martin Perner <e0725782@student.tuwien.ac.at>
+--  Copyright (C) 2010 Stefan Rebernig <stefan.rebernig@gmail.com>
+--  Copyright (C) 2010 Manfred Schwarz <e0725898@student.tuwien.ac.at>
+--  Copyright (C) 2010 Bernhard Urban <lewurm@gmail.com>
+--
+--  This program is free software: you can redistribute it and/or modify
+--  it under the terms of the GNU General Public License as published by
+--  the Free Software Foundation, either version 3 of the License, or
+--  (at your option) any later version.
+--
+--  This program is distributed in the hope that it will be useful,
+--  but WITHOUT ANY WARRANTY; without even the implied warranty of
+--  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+--  GNU General Public License for more details.
+--
+--  You should have received a copy of the GNU General Public License
+--  along with this program.  If not, see <http://www.gnu.org/licenses/>.
+
 library ieee;
 
 use IEEE.std_logic_1164.all;
@@ -10,26 +31,20 @@ architecture behaviour of r_w_ram is
 	subtype RAM_ENTRY_TYPE is std_logic_vector(DATA_WIDTH -1 downto 0);
 	type RAM_TYPE is array (0 to (2**ADDR_WIDTH)-1) of RAM_ENTRY_TYPE;
 	
-	signal ram : RAM_TYPE := (--0 => "11100000000000011001000000000000",  -- r0 = r3 + r2 (always)
-				--  1 => "11100101000000001000100000000000",  -- r0 = r1 << 0 (always)
-				--  2 => "11100000000010000001100000000000",  -- r1 = r0 + r3 (always)
-				--  3 => "11100000101000000001000000000000",
-				--  4 => "11100001000110010111011001101100", 
-				  0 => "11101100000000001000000000000000", -- cmp r0 , r1 
-				  1 => "00000000000100000000100000000000",
-				  2 => "00000000001110000001000000000000",
-				  3 => "11100001000110010000011001101100", 
-				  others => x"F0000000");
-
+	signal ram : RAM_TYPE := (others => x"00000000");
+	
 begin
 	process(clk)
 	begin
 		if rising_edge(clk) then
-			data_out <= ram(to_integer(UNSIGNED(rd_addr)));
+		 data_out <= ram(to_integer(UNSIGNED(rd_addr)));
+
+
 			
 			if wr_en = '1' then
 				ram(to_integer(UNSIGNED(wr_addr))) <= data_in;
 			end if;
 		end if;
 	end process;
+	
 end architecture behaviour;