X-Git-Url: http://wien.tomnetworks.com/gitweb/?a=blobdiff_plain;f=cpu%2Fsrc%2Fr_w_ram_b.vhd;h=81682bb7bbb500650e1eed6695da51097d5112ab;hb=f8e429a38c3349e4b5578c367e5494a30b42e662;hp=4f1a0e0e8d8080bf4ea0e40e91ca9e46c06873fb;hpb=7c9e2f34172a9a04aeef756f914203b58c935043;p=calu.git

diff --git a/cpu/src/r_w_ram_b.vhd b/cpu/src/r_w_ram_b.vhd
index 4f1a0e0..81682bb 100644
--- a/cpu/src/r_w_ram_b.vhd
+++ b/cpu/src/r_w_ram_b.vhd
@@ -12,13 +12,96 @@ architecture behaviour of r_w_ram is
 	
 									-- r0 = 0, r1 = 1, r2 = 3, r3 = A
 
-	signal ram : RAM_TYPE := (  0 => "11100001000010001000000000111000", -- r1 = 7
-				    1 => "11100001000100010000000000101000", -- r2 = 5
-				    2 => "11100001000110011000000000100000", -- r3 = 4
-				    3 => "11100000001000010001100000000000", -- r4 = r2 + r3
-				    4 => "11100010001010100000100000000000", -- r5 = r4 and r1
+	signal ram : RAM_TYPE := (
+	--	0 =>  x"ed2802d0", -- ldi r5, 0x5a;;
+	--		1 =>  x"ed010058", -- ldi r0, 0x200b;;
+	--		2 =>  x"e7a80000", -- stw r5, 0(r0);;
+	--		3 =>  x"e7828000", -- stw r0, 0(r5);;
+	--		4 =>  "11101011000000000000000000000010",
+
+			--8 => "11100111100010000000000000000000", --stw
+--	0 => "11101101000000000000000000000000",	--ldi
+--	1 => "11101101001000000000000000000000",	--ldi
+--	2 => "11100111101000000000000000000000",	--stw
+--	3 => "11100001000000000000000000100001",
+--	4 => "11101100100000000000001100000000",
+--	5 => "00001011011111111111111010000011",
+--	6 => "11101101000000000000000000001000",
+--	7 => "11100111100000000000000000001111",
+--	8 => "11100111100000000000000000010011",
+
+--	9 => x"ed080048",	--;ldi r1, 9;;
+--	10 => x"ed500080",	--;ldil r10, list@lo ;; global pointer
+--	11 => x"fd500002",	--;ldih r10, list@hi;;
+--	12 => x"eb000107",	--;call+ fibcall;;
+	--13 => x"eb7ffe03",	--;br+ main;;
+--	13 => "11101011000000000000000000000010",	-- endless loop	--2; fib(n) {
+			--2;   if (list[n] > 0) {
+			--2;   	return list[n]
+			--2;   }
+			--2;   a = fib(n-1)
+			--2;   list[n] = a + list[n-2]
+			--2;   return list[n]
+			--2; }
+			--3;fibcall;
+			--2;update counter for aligned access
+--	14 => x"e5088800",	--;lls r1, r1, 2 ;; *4
+			--2;calculate adress of top element
+--	15 => x"e0150800",	--;add r2, r10, r1;;
+			--3;fibmem;
+			--2;load top element
+--	16 => x"e7010000",	--;ldw r0, 0(r2);;
+			--2;compare if set
+--	17 => x"ec800000",	--;cmpi r0, 0;;
+			--2;return if set
+--	18 => x"0b000008",	--;retnz-;;
+			--2;decrement adress for next lopp
+--	19 => x"e1910020",	--;subi r2, r2, 4;;
+			--2;iterative call for n-1 element
+--	20 => x"eb7ffe07",	--;call+ fibmem;;
+			--2;load n-2 element
+--	21 => x"e7197ffc",	--;ldw r3, 0-4(r2);;
+			--2;add n-1 and n-2 element
+--	22 => x"e0018000",	--;add r0, r3, r0;;
+			--2;increment address for n element
+			--2;is needed because after return
+			--2;we need r2 to be set to the address
+			--2;of element n
+--	23 => x"e1110020",	--;addi r2, r2, 4;;
+			--2;store fib n
+--	24 => x"e7810000",	--;stw r0, 0(r2);;
+--	25 => x"eb00000a",	--;ret+;;
+
+-- 1 1 2 3 5 8 13 21 34	55			   
+
+
 				  others => x"F0000000");
 
+--	signal ram : RAM_TYPE := (  0 => "11101101000000000000000000000000", -- r0 = 0
+--
+--				    1 => "11101101000010000000000000111000", -- r1 = 7
+--				    2 => "11101101000100000000000000101000", -- r2 = 5
+--				    3 => "11101101000110000000000000100000", -- r3 = 4
+--				    4 => "11100000001000010001100000000000", -- r4 = r2 + r3
+--				    5 => "11100010001010100000100000000000", -- r5 = r4 and r1
+--
+--				    6 => "11100001000000000000000000001000", -- r0 = r0 + 1
+--				    7 => "11101100100000000000000000011000", -- cmpi r0 , 2      
+--
+--				    8 => "00001011011111111111110010000111", -- jump -7
+--				    9 => "11101011000000000000000010000010", -- jump +1
+--				   --10 => "11101011000000000000000010000010", -- jump +1
+--
+  --                                 10 => "11100111101010100000000000000001", -- stw r5,r4,1
+	--		 	   11 => "11101100001000100000000000000000", -- cmp r4 , r4       => 2-2 => 1001
+--
+--				   12 => "11101011000000000000000000000010", -- jump +0
+
+				   
+
+
+--				  others => x"F0000000");
+
 --	signal ram : RAM_TYPE := (  0 => "11100000000100001000000000000000", --add r2, r1, r0    => r2 = 1
 --				    1 => "11100000000110001000000000000000", --add r3, r1, r0    => r3 = 1
 --				    2 => "11100000001000011001000000000000", --add r4, r3, r2    => r4 = 2
@@ -46,7 +129,13 @@ begin
 	process(clk)
 	begin
 		if rising_edge(clk) then
-			data_out <= ram(to_integer(UNSIGNED(rd_addr)));
+	--	 data_out <= ram(to_integer(UNSIGNED(rd_addr)));
+			case rd_addr is
+				when "00000000000" => data_out <= x"ed2802d0"; -- ldi r5, 0x5a;;
+				when "00000000001" => data_out <= x"ed010058"; -- ldi r0, 0x200b;;
+				when "00000000010" => data_out <= x"e7a80000"; -- stw r5, 0(r0);;
+				when others => data_out <= "11101011000000000000000000000010";
+			end case;
 			
 			if wr_en = '1' then
 				ram(to_integer(UNSIGNED(wr_addr))) <= data_in;