X-Git-Url: http://wien.tomnetworks.com/gitweb/?a=blobdiff_plain;f=cpu%2Fsrc%2Fpipeline_tb.vhd;h=eda81023058f86351b0850bded6ddccc83fd102a;hb=250b78e68b59bb5639dba5f0f3e2b23cbe71f823;hp=e396a6bd78f74079dde3c37d25edb765f2c4b735;hpb=64ef7ca2830116409f4c23802a202ab4b1ce5ec8;p=calu.git

diff --git a/cpu/src/pipeline_tb.vhd b/cpu/src/pipeline_tb.vhd
index e396a6b..eda8102 100644
--- a/cpu/src/pipeline_tb.vhd
+++ b/cpu/src/pipeline_tb.vhd
@@ -59,7 +59,10 @@ architecture behavior of pipeline_tb is
 		 signal cycle_cnt : integer;
 
 		signal sseg0, sseg1, sseg2, sseg3 : std_logic_vector(0 to 6);
+		signal int_req_pin : interrupt_t;
 
+		signal new_im_data :std_logic;
+		signal im_addr, im_data : gp_register_t;
 
 begin
 
@@ -89,16 +92,20 @@ begin
 		--System inputs
 			clk => sys_clk_pin, --: in std_logic;
 			reset => sys_res_n_pin, --: in std_logic;
-		
+			s_reset => '0',
 		--Data inputs
 			jump_result => jump_result_pin, --: in instruction_addr_t;
 			prediction_result => prediction_result_pin, --: in instruction_addr_t;
 			branch_prediction_bit => branch_prediction_bit_pin,  --: in std_logic;
 			alu_jump_bit => alu_jump_bit_pin, --: in std_logic;
+			new_im_data_in => new_im_data,
+			im_addr => im_addr,
+			im_data => im_data,
 
 		--Data outputs
 			instruction => instruction_pin, --: out instruction_word_t
-			prog_cnt => prog_cnt
+			prog_cnt => prog_cnt,
+			int_req => int_req_pin
 		);	
 
 	decode_st : decode_stage
@@ -134,10 +141,10 @@ begin
                 data_pin, alu_jump_pin,brpr_pin, wr_en_pin, dmem_pin,dmem_wr_en_pin,hword_pin,byte_s_pin, gpm_out_pin);
 
           writeback_st : writeback_stage
-                generic map('0', '1')
+                generic map('0', '1', "altera",50)
                 port map(sys_clk_pin, sys_res_n_pin, result_pin, result_addr_pin, addr_pin, data_pin, alu_jump_pin, brpr_pin, 
                 wr_en_pin, dmem_pin, dmem_wr_en_pin, hword_pin, byte_s_pin,
-                reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, jump_result_pin, alu_jump_bit_pin, tx_pin, rx_pin, sseg0, sseg1, sseg2, sseg3);
+                reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, jump_result_pin, alu_jump_bit_pin, tx_pin, rx_pin, new_im_data, im_addr, im_data, sseg0, sseg1, sseg2, sseg3, int_req_pin);
 
 
 
@@ -184,9 +191,11 @@ begin
 	begin
 		for i in 0 to 9 loop
 			rx_pin <= trans_data(i);
+			report "bit: " & std_logic'image(trans_data(i));
 			dummy <= not dummy;
 			wait on dummy;
-			icwait(BAUD_COUNT);
+			-- icwait(BAUD_COUNT);
+			icwait(50);
 		end loop;
 	end txd;
 
@@ -196,6 +205,7 @@ begin
     -- initial reset
     -----------------------------------------------------------------------------
 	sys_res_n_pin <= '0';
+	rx_pin <= '1';
 --	reg_w_addr_pin <= (others => '0');
 --	reg_wr_data_pin <= (others => '0');
 --	reg_we_pin <= '0';
@@ -207,9 +217,12 @@ begin
 	
 	icwait(10);
 
-	txd("0100000101");
+	txd("0000100101");
+	icwait(600);
+	icwait(600);
 
-	icwait(1000000000);
+	txd("0000100101");
+	icwait(600000000);
 
     ---------------------------------------------------------------------------
     -- exit testbench