X-Git-Url: http://wien.tomnetworks.com/gitweb/?a=blobdiff_plain;f=cpu%2Fsrc%2Fpipeline_tb.vhd;h=870c38d7e442a3c679ce690238bfa2594c9abdc9;hb=1968f329b10681b760faec9369aa893cd2af8d44;hp=0bdcaca896d5b82b17fbbe6bd911ecbdec7fe861;hpb=59b64378e94e8db6225a30c8d62e7472c66f675b;p=calu.git

diff --git a/cpu/src/pipeline_tb.vhd b/cpu/src/pipeline_tb.vhd
index 0bdcaca..870c38d 100644
--- a/cpu/src/pipeline_tb.vhd
+++ b/cpu/src/pipeline_tb.vhd
@@ -1,3 +1,24 @@
+--   `Deep Thought', a softcore CPU implemented on a FPGA
+--
+--  Copyright (C) 2010 Markus Hofstaetter <markus.manrow@gmx.at>
+--  Copyright (C) 2010 Martin Perner <e0725782@student.tuwien.ac.at>
+--  Copyright (C) 2010 Stefan Rebernig <stefan.rebernig@gmail.com>
+--  Copyright (C) 2010 Manfred Schwarz <e0725898@student.tuwien.ac.at>
+--  Copyright (C) 2010 Bernhard Urban <lewurm@gmail.com>
+--
+--  This program is free software: you can redistribute it and/or modify
+--  it under the terms of the GNU General Public License as published by
+--  the Free Software Foundation, either version 3 of the License, or
+--  (at your option) any later version.
+--
+--  This program is distributed in the hope that it will be useful,
+--  but WITHOUT ANY WARRANTY; without even the implied warranty of
+--  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+--  GNU General Public License for more details.
+--
+--  You should have received a copy of the GNU General Public License
+--  along with this program.  If not, see <http://www.gnu.org/licenses/>.
+
 library IEEE;
 use IEEE.std_logic_1164.all;
 use IEEE.numeric_std.all;
@@ -92,7 +113,7 @@ begin
 		--System inputs
 			clk => sys_clk_pin, --: in std_logic;
 			reset => sys_res_n_pin, --: in std_logic;
-		
+			s_reset => '1',
 		--Data inputs
 			jump_result => jump_result_pin, --: in instruction_addr_t;
 			prediction_result => prediction_result_pin, --: in instruction_addr_t;
@@ -141,7 +162,7 @@ begin
                 data_pin, alu_jump_pin,brpr_pin, wr_en_pin, dmem_pin,dmem_wr_en_pin,hword_pin,byte_s_pin, gpm_out_pin);
 
           writeback_st : writeback_stage
-                generic map('0', '1')
+                generic map('0', '1', "altera",50)
                 port map(sys_clk_pin, sys_res_n_pin, result_pin, result_addr_pin, addr_pin, data_pin, alu_jump_pin, brpr_pin, 
                 wr_en_pin, dmem_pin, dmem_wr_en_pin, hword_pin, byte_s_pin,
                 reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, jump_result_pin, alu_jump_bit_pin, tx_pin, rx_pin, new_im_data, im_addr, im_data, sseg0, sseg1, sseg2, sseg3, int_req_pin);
@@ -191,9 +212,11 @@ begin
 	begin
 		for i in 0 to 9 loop
 			rx_pin <= trans_data(i);
+			report "bit: " & std_logic'image(trans_data(i));
 			dummy <= not dummy;
 			wait on dummy;
-			icwait(BAUD_COUNT);
+			-- icwait(BAUD_COUNT);
+			icwait(50);
 		end loop;
 	end txd;
 
@@ -203,6 +226,7 @@ begin
     -- initial reset
     -----------------------------------------------------------------------------
 	sys_res_n_pin <= '0';
+	rx_pin <= '1';
 --	reg_w_addr_pin <= (others => '0');
 --	reg_wr_data_pin <= (others => '0');
 --	reg_we_pin <= '0';
@@ -214,9 +238,12 @@ begin
 	
 	icwait(10);
 
-	txd("0100000101");
+	txd("0000100101");
+	icwait(600);
+	icwait(600);
 
-	icwait(1000000000);
+	txd("0000100101");
+	icwait(600000000);
 
     ---------------------------------------------------------------------------
     -- exit testbench