X-Git-Url: http://wien.tomnetworks.com/gitweb/?a=blobdiff_plain;f=cpu%2Fsrc%2Fpipeline_tb.vhd;h=8539c425f568c71fc42d6381affabb26a14fd5e9;hb=b333da851dda456b48f2a2535c4aeba143c657e1;hp=fd86d721e9910f178d5ed2f58e90a803241d47d6;hpb=c22560759ba6cbf74fc32fc5b20609156942ee0f;p=calu.git diff --git a/cpu/src/pipeline_tb.vhd b/cpu/src/pipeline_tb.vhd index fd86d72..8539c42 100644 --- a/cpu/src/pipeline_tb.vhd +++ b/cpu/src/pipeline_tb.vhd @@ -48,12 +48,16 @@ architecture behavior of pipeline_tb is signal dmem_pin : std_logic;--memop signal dmem_wr_en_pin : std_logic; signal hword_pin : std_logic; - signal byte_s_pin : std_logic; + signal byte_s_pin, tx_pin : std_logic; signal gpm_in_pin : extmod_rec; signal gpm_out_pin : gp_register_t; signal nop_pin : std_logic; + signal cycle_cnt : integer; + + signal sseg0, sseg1, sseg2, sseg3 : std_logic_vector(0 to 6); + begin @@ -131,7 +135,7 @@ begin generic map('0', '1') port map(sys_clk_pin, sys_res_n_pin, result_pin, result_addr_pin, addr_pin, data_pin, alu_jump_pin, brpr_pin, wr_en_pin, dmem_pin, dmem_wr_en_pin, hword_pin, byte_s_pin, - reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, jump_result_pin, alu_jump_bit_pin); + reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, jump_result_pin, alu_jump_bit_pin, tx_pin, sseg0, sseg1, sseg2, sseg3); @@ -149,6 +153,18 @@ begin wait for cc/2; end process CLKGEN; + + cnt : process(sys_clk_pin, sys_res_n_pin) + + begin + + if (sys_res_n_pin = '0') then + cycle_cnt <= 0; + elsif (sys_clk_pin'event and sys_clk_pin = '1') then + cycle_cnt <= cycle_cnt + 1; + end if; + + end process cnt; ------------------------------------------------------------------------------- -- test the design ------------------------------------------------------------------------------- @@ -177,7 +193,7 @@ begin wait until sys_res_n_pin = '1'; - icwait(100000); + icwait(1000000000); --------------------------------------------------------------------------- -- exit testbench